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259 lines
10 KiB
YAML
259 lines
10 KiB
YAML
# ########################################################################
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# Copyright (C) 2024-2025 Advanced Micro Devices, Inc. All rights Reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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#
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# ########################################################################
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# Template used to process YAML from log files
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---
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include: rocsparse_common.yaml
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#include: known_bugs.yaml
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# This is a minimal smoke test of rocsparse functionality
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# It will run at least a single small sized function test for all of the functions.
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# Algorithm variations controlled by enums will be tested but those that are selected by size will not be
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# exhaustive as very small sizes are only used
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Definitions:
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- &common
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M: 1
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N: 1
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K: 1
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storage: [rocsparse_storage_mode_sorted]
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direction: [rocsparse_direction_row]
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transB: [rocsparse_operation_none]
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diag: [rocsparse_diag_type_non_unit]
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apol: [rocsparse_analysis_policy_reuse]
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spol: [rocsparse_solve_policy_auto]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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matrix_type: [rocsparse_matrix_type_general]
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- &alpha_beta
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- { alpha: 1.0, beta: -1.0, alphai: 1.0, betai: -0.5 }
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- { alpha: -0.5, beta: 0.5, alphai: -0.5, betai: 1.0 }
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Tests:
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#################################################################################
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# SpMV in CSR format #
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#################################################################################
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# We test this, as it is most important algorithm in rocsparse. #
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# There is no special hardware requirements. It uses LDS and atomicAdd(fp32/64) #
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# in some rare cases. Atomics are agent wide. #
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#################################################################################
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- name: level2_spmv_csr_real
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category: pre_checkin
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function: spmv_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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<<: *common
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transA: [rocsparse_operation_none, rocsparse_operation_transpose]
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alpha_beta: *alpha_beta
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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filename: [nos4]
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- name: level2_spmv_csr_complex
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category: pre_checkin
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function: spmv_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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<<: *common
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transA: [rocsparse_operation_none, rocsparse_operation_conjugate_transpose]
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alpha_beta: *alpha_beta
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spmv_alg: [rocsparse_spmv_alg_csr_rowsplit, rocsparse_spmv_alg_csr_lrb]
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filename: [Chevron2]
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- name: level2_v2_spmv_csr_real
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category: pre_checkin
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function: v2_spmv_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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<<: *common
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transA: [rocsparse_operation_none, rocsparse_operation_transpose]
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alpha_beta: *alpha_beta
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spmv_alg: [rocsparse_spmv_alg_csr_rowsplit]
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filename: [nos4]
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- name: level2_v2_spmv_csr_real
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category: pre_checkin
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function: v2_spmv_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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<<: *common
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transA: [rocsparse_operation_none]
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alpha_beta: *alpha_beta
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive]
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filename: [nos4]
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- name: level2_v2_spmv_csr_complex
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category: pre_checkin
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function: v2_spmv_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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<<: *common
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transA: [rocsparse_operation_none, rocsparse_operation_conjugate_transpose]
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alpha_beta: *alpha_beta
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spmv_alg: [rocsparse_spmv_alg_csr_rowsplit]
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filename: [Chevron2]
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- name: level2_v2_spmv_csr_complex
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category: pre_checkin
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function: v2_spmv_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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<<: *common
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transA: [rocsparse_operation_none]
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alpha_beta: *alpha_beta
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spmv_alg: [rocsparse_spmv_alg_csr_lrb]
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filename: [Chevron2]
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#################################################################################
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# SpSV in CSR format #
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#################################################################################
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# Algorithm has internal dependencies within the matrix and uses spin looping #
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# to wait until data dependencies have been resolved by other wavefronts / work #
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# groups. The spin loop repeatedly querries the status by using atomic_load #
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# (relaxed) from global memory. Once a dependency has been resolved, it is #
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# stored in global memory using atomic_store (release). Atomics are agent wide. #
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#################################################################################
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- name: level2_spsv_csr_real
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category: pre_checkin
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function: spsv_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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<<: *common
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alpha_alphai: *alpha_beta
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uplo: [rocsparse_fill_mode_lower, rocsparse_fill_mode_upper]
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filename: [mac_econ_fwd500]
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- name: level2_spsv_csr_complex
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category: pre_checkin
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function: spsv_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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<<: *common
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alpha_alphai: *alpha_beta
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transA: [rocsparse_operation_conjugate_transpose]
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uplo: [rocsparse_fill_mode_lower, rocsparse_fill_mode_upper]
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filename: [Chevron2]
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#################################################################################
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# SpGEMM in CSR format #
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#################################################################################
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# This algorithm uses hash tables to merge two matrix rows. It makes extensive #
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# use of workgroup-wide atomicCAS in LDS. #
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#################################################################################
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- name: extra_spgemm_csr_real
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category: pre_checkin
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function: spgemm_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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<<: *common
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N: [13, 523]
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alpha_beta: *alpha_beta
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filename: [nos4]
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- name: extra_spgemm_csr_complex
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category: pre_checkin
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function: spgemm_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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<<: *common
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N: [21, 719]
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alpha_beta: *alpha_beta
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filename: [Chevron2]
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#################################################################################
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# SpGEAM in CSR format #
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#################################################################################
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# This algorithm uses hash tables to merge two matrix rows. It makes extensive #
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# use of workgroup-wide atomicCAS in LDS. #
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#################################################################################
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- name: extra_spgeam_csr_real
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category: pre_checkin
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function: spgeam_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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<<: *common
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N: [13, 523]
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alpha_beta: *alpha_beta
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filename: [nos4]
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- name: extra_spgeam_csr_complex
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category: pre_checkin
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function: spgeam_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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<<: *common
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N: [21, 719]
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alpha_beta: *alpha_beta
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filename: [Chevron2]
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#################################################################################
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# csrilusv in CSR format #
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#################################################################################
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# Combination of multiple spin-looping algorithms that depend on each other. #
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# Part of this algorithm spin-loops also on LDS. #
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#################################################################################
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- name: precond_csrilusv_csr_real
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category: pre_checkin
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function: csrilusv
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precision: *single_double_precisions
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<<: *common
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filename: [mac_econ_fwd500]
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- name: precond_csrilusv_csr_complex
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category: pre_checkin
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function: csrilusv
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precision: *single_double_precisions_complex
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<<: *common
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filename: [Chevron2]
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#################################################################################
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# SpMM in CSR format #
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#################################################################################
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# Similar to csrmv, this algorithm is one of the most important ones in #
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# rocsparse. It uses LDS but there is nothing special in terms of hardware #
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# requirements. #
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#################################################################################
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- name: level3_spmm_csr_real
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category: pre_checkin
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function: spmm_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions
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<<: *common
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N: [4, 19, 73]
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transA: [rocsparse_operation_none, rocsparse_operation_transpose]
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transB: [rocsparse_operation_none, rocsparse_operation_transpose]
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filename: [nos4]
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- name: level3_spmm_csr_complex
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category: pre_checkin
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function: spmm_csr
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indextype: *i32i32_i64i32_i64i64
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precision: *single_double_precisions_complex
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<<: *common
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N: [3, 21]
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transA: [rocsparse_operation_none, rocsparse_operation_conjugate_transpose]
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transB: [rocsparse_operation_none, rocsparse_operation_conjugate_transpose]
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filename: [Chevron2]
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