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497 lines
24 KiB
C++
497 lines
24 KiB
C++
// Copyright Advanced Micro Devices, Inc., or its affiliates.
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// SPDX-License-Identifier: MIT
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#include <rocRoller/DataTypes/DataTypes.hpp>
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#include <rocRoller/GPUArchitecture/GPUArchitectureTarget.hpp>
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#include <rocRoller/InstructionValues/Register.hpp>
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#include <rocRoller/KernelOptions_detail.hpp>
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#include <catch2/catch_test_macros.hpp>
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#include <catch2/generators/catch_generators.hpp>
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#include <catch2/matchers/catch_matchers_string.hpp>
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#include "common/Utilities.hpp"
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#include "TestContext.hpp"
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using namespace rocRoller;
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namespace WMMAObserverTests
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{
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class WMMAObserverTest : public TestContext
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{
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public:
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WMMAObserverTest(GPUArchitectureGFX gfx)
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: TestContext(TestContext::ForTarget({gfx})){};
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WMMAObserverTest(GPUArchitectureTarget target, KernelOptions kernelOptions)
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: TestContext(TestContext::ForTarget(target, kernelOptions)){};
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void peekAndSchedule(Instruction& inst, uint expectedNops = 0)
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{
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auto peeked = m_context->observer()->peek(inst);
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CHECK(peeked.nops == expectedNops);
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m_context->schedule(inst);
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}
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};
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TEST_CASE("RAW hazards on GFX1200/GFX1201", "[codegen]")
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{
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auto target = GENERATE(GPUArchitectureGFX::GFX1200, GPUArchitectureGFX::GFX1201);
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WMMAObserverTest t{target};
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{ // A/B is previous D
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const auto v0 = t.createRegisters(Register::Type::Vector, DataType::Half, 5);
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const auto v1 = t.createRegisters(Register::Type::Vector, DataType::Half, 1, 2);
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SECTION("Expect one V_NOP If the second WMMA's A is the first WMMA's D")
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{
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std::vector<Instruction> insts = {Instruction("v_wmma_f16_16x16x16_f16",
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{v1[0]->subset({0, 1})},
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{v0[0], v0[1], v0[2]},
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{},
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""),
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Instruction("v_wmma_f16_16x16x16_f16",
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{v0[3]},
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{v1[0]->subset({0, 1}), v0[4], v0[3]},
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{},
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""),
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Instruction("s_endpgm", {}, {}, {}, "")};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], 1);
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CHECK(1 == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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SECTION("Expect one V_NOP If the second WMMA's B is the first WMMA's D")
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{
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std::vector<Instruction> insts = {Instruction("v_wmma_f16_16x16x16_f16",
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{v1[0]->subset({0, 1})},
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{v0[0], v0[1], v0[2]},
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{},
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""),
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Instruction("v_wmma_f16_16x16x16_f16",
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{v0[3]},
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{v1[0]->subset({0, 1}), v0[4], v0[3]},
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{},
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""),
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Instruction("s_endpgm", {}, {}, {}, "")};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], 1);
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CHECK(1 == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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}
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{ // A/B overlap with D
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const auto v0 = t.createRegisters(Register::Type::Vector, DataType::Half, 6);
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const auto v1 = t.createRegisters(Register::Type::Vector, DataType::Half, 1, 3);
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SECTION("Expect one V_NOP If the second WMMA's A overlaps with the first WMMA's D")
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{
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std::vector<Instruction> insts = {Instruction("v_wmma_f16_16x16x16_f16",
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{v1[0]->subset({0, 1})},
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{v0[0], v0[1], v0[2]},
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{},
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""),
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Instruction("v_wmma_f16_16x16x16_f16",
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{v0[3]},
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{v1[0]->subset({1, 2}), v0[4], v0[5]},
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{},
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""),
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Instruction("s_endpgm", {}, {}, {}, "")};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], 1);
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CHECK(1 == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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SECTION("Expect one V_NOP If the second WMMA's B overlaps with the first WMMA's D")
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{
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// If the second WMMA's B overlaps the first WMMA's D then one V_NOP is expected
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std::vector<Instruction> insts = {Instruction("v_wmma_f16_16x16x16_f16",
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{v1[0]->subset({0, 1})},
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{v0[0], v0[1], v0[2]},
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{},
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""),
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Instruction("v_wmma_f16_16x16x16_f16",
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{v0[3]},
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{v0[4], v1[0]->subset({1, 2}), v0[5]},
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{},
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""),
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Instruction("s_endpgm", {}, {}, {}, "")};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], 1);
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CHECK(1 == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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}
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SECTION("No register overlap should no be a hazard")
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{
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const auto v0 = t.createRegisters(Register::Type::Vector, DataType::Half, 4);
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const auto v1 = t.createRegisters(Register::Type::Vector, DataType::Half, 1, 4);
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std::vector<Instruction> insts = {Instruction("v_wmma_f16_16x16x16_f16",
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{v1[0]->subset({0, 1})},
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{v0[0], v0[1], v1[0]->subset({0, 1})},
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{},
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""),
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Instruction("v_wmma_f16_16x16x16_f16",
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{v1[0]->subset({2, 3})},
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{v0[2], v0[3], v1[0]->subset({2, 3})},
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{},
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""),
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Instruction("s_endpgm", {}, {}, {}, "")};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1]);
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CHECK(0 == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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}
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TEST_CASE("WAR/WAW hazards on GFX1200/GFX1201", "[codegen]")
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{
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auto target = GENERATE(GPUArchitectureGFX::GFX1200, GPUArchitectureGFX::GFX1201);
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WMMAObserverTest t{target};
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const auto v0 = t.createRegisters(Register::Type::Vector, DataType::Half, 4);
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const auto v1 = t.createRegisters(Register::Type::Vector, DataType::Float, 1, 4);
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const auto v2 = t.createRegisters(Register::Type::Vector, DataType::Float, 1);
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SECTION("WMMA writes D then VALU reads D")
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{
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std::vector<Instruction> insts = {
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Instruction("v_wmma_f32_16x16x16_f16",
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{v1[0]->subset({0, 1})},
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{v0[0], v0[1], v1[0]->subset({0, 1})},
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{},
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""),
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Instruction("v_add_f32", {v2[0]}, {v2[0], v1[0]->subset({0})}, {}, ""),
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Instruction("s_endpgm", {}, {}, {}, ""),
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};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], 8);
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CHECK(8 == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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SECTION("WMMA writes D then VALU writes D")
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{
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std::vector<Instruction> insts = {
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Instruction("v_wmma_f32_16x16x16_f16",
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{v1[0]->subset({0, 1})},
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{v0[0], v0[1], v1[0]->subset({0, 1})},
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{},
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""),
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Instruction("v_add_f32", {v1[0]->subset({0})}, {v2[0], v2[0]}, {}, ""),
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Instruction("s_endpgm", {}, {}, {}, ""),
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};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], 8);
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CHECK(8 == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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}
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TEST_CASE("RAW hazards on GFX1250", "[codegen]")
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{
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const auto target = GENERATE(GPUArchTargetGFX1250Rev0, GPUArchTargetGFX1250Rev1);
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const auto coexecutionEnabled = GENERATE(true, false);
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KernelOptions kernelOptions{};
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kernelOptions->coexecutionEnabled = coexecutionEnabled;
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WMMAObserverTest t{target, kernelOptions};
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const auto FC = Register::AllocationOptions::FullyContiguous();
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SECTION("Expect 1 + coexecSlots V_NOP(s) if second WMMA's A is first WMMA's D and A && B "
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"are *NOT* F8")
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{
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const auto v = t.createRegisters(Register::Type::Vector, DataType::Half, 5, 8, FC);
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// coexecSlots = 4, if first WMMA is not:
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// - v_wmma*_iu8; and
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// - v_wmma*_iu4; and
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// - v_wmma*f8f6f4 && A and B are not F8
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const auto expectedVNops = 1 + (coexecutionEnabled ? 4 : 0);
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std::vector<Instruction> insts
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= {Instruction("v_wmma_f16_16x16x32_f16", {v[0]}, {v[1], v[2], v[3]}, {}, ""),
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Instruction("v_wmma_f16_16x16x32_f16", {v[4]}, {v[0], v[2], v[3]}, {}, ""),
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Instruction("s_endpgm", {}, {}, {}, "")};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], expectedVNops);
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CHECK(expectedVNops == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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SECTION("Expect 1 + coexecSlots V_NOP(s) if second WMMA's A is first WMMA's D and A"
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"*IS* F8")
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{
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const auto [wmmaInst, types, regCounts] = GENERATE(
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std::make_tuple(std::string{"v_wmma_f32_16x16x128_f8f6f4"},
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std::make_tuple(DataType::Float, DataType::FP8x4, DataType::FP4x8),
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std::make_tuple(8, 16, 8)),
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std::make_tuple(std::string{"v_wmma_i32_16x16x64_iu8"},
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std::make_tuple(DataType::Int32, DataType::Int32, DataType::Int32),
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std::make_tuple(8, 8, 8)),
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std::make_tuple(std::string{"v_wmma_f32_32x16x128_f4"},
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std::make_tuple(DataType::Float, DataType::FP4x8, DataType::FP4x8),
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std::make_tuple(16, 16, 8)));
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const auto [v0_dt, vA_dt, vB_dt] = types;
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const auto [v0_count, vA_count, vB_count] = regCounts;
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const auto v0 = t.createRegisters(Register::Type::Vector, v0_dt, 3, v0_count, FC);
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const auto vA = t.createRegisters(Register::Type::Vector, vA_dt, 2, vA_count, FC);
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const auto vB = t.createRegisters(Register::Type::Vector, vB_dt, 2, vB_count, FC);
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// coexecSlots = 8, if first WMMA is:
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// - v_wmma*_iu8; or
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// - v_wmma*_iu4; or
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// - v_wmma*f8f6f4 && A or B is F8;
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// - v_wmma*_f4
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const auto expectedVNops = 1 + (coexecutionEnabled ? 8 : 0);
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std::vector<Instruction> insts
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= {Instruction(wmmaInst, {v0[0]}, {vA[0], vB[0], v0[1]}, {}, ""),
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Instruction(wmmaInst, {v0[2]}, {vA[1], vB[1], v0[0]}, {}, ""),
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Instruction("s_endpgm", {}, {}, {}, "")};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], expectedVNops);
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CHECK(expectedVNops == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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SECTION(
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"Expect 0 + coexecSlots V_NOP(s) if VALU reads D after WMMA and A && B are *NOT* F8")
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{
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const auto v = t.createRegisters(Register::Type::Vector, DataType::Half, 5, 8, FC);
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// coexecSlots = 4, if first WMMA is not:
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// - v_wmma*_iu8; and
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// - v_wmma*_iu4; and
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// - v_wmma*f8f6f4 && A and B are not F8
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const auto expectedVNops = 0 + (coexecutionEnabled ? 4 : 0);
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std::vector<Instruction> insts
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= {Instruction("v_wmma_f16_16x16x32_f16", {v[0]}, {v[1], v[2], v[3]}, {}, ""),
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Instruction("v_add_f16",
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{v[4]->subset({0})},
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{v[0]->subset({1}), v[4]->subset({1})},
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{},
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""),
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Instruction("s_endpgm", {}, {}, {}, "")};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], expectedVNops);
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CHECK(expectedVNops == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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SECTION("Expect 0 + coexecSlots V_NOP(s) if VALU reads D after WMMA and A *IS* F8")
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{
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const auto [wmmaInst, types, regCounts] = GENERATE(
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std::make_tuple(std::string{"v_wmma_f32_16x16x128_f8f6f4"},
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std::make_tuple(DataType::Float, DataType::FP8x4, DataType::FP4x8),
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std::make_tuple(8, 16, 8)),
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std::make_tuple(std::string{"v_wmma_i32_16x16x64_iu8"},
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std::make_tuple(DataType::Int32, DataType::Int32, DataType::Int32),
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std::make_tuple(8, 8, 8)),
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std::make_tuple(std::string{"v_wmma_f32_32x16x128_f4"},
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std::make_tuple(DataType::Float, DataType::FP4x8, DataType::FP4x8),
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std::make_tuple(16, 16, 8)));
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const auto [v0_dt, vA_dt, vB_dt] = types;
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const auto [v0_count, vA_count, vB_count] = regCounts;
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const auto v0 = t.createRegisters(Register::Type::Vector, v0_dt, 3, v0_count, FC);
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const auto vA = t.createRegisters(Register::Type::Vector, vA_dt, 1, vA_count, FC);
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const auto vB = t.createRegisters(Register::Type::Vector, vB_dt, 1, vB_count, FC);
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// coexecSlots = 8, if first WMMA is:
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// - v_wmma*_iu8; or
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// - v_wmma*_iu4; or
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// - v_wmma*f8f6f4 && A or B is F8
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const auto expectedVNops = 0 + (coexecutionEnabled ? 8 : 0);
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std::vector<Instruction> insts
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= {Instruction(wmmaInst, {v0[0]}, {vA[0], vB[0], v0[1]}, {}, ""),
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Instruction("v_add_f16",
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{v0[2]->subset({0})},
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{v0[0]->subset({1}), v0[2]->subset({1})},
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{},
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""),
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Instruction("s_endpgm", {}, {}, {}, "")};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], expectedVNops);
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CHECK(expectedVNops == countSubstring(t.output(), "v_nop"));
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t.output().clear();
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}
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}
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TEST_CASE("WAR/WAW hazards on GFX1250", "[codegen]")
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{
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const auto target = GENERATE(GPUArchTargetGFX1250Rev0, GPUArchTargetGFX1250Rev1);
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const auto coexecutionEnabled = GENERATE(true, false);
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KernelOptions kernelOptions{};
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kernelOptions->coexecutionEnabled = coexecutionEnabled;
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WMMAObserverTest t{target, kernelOptions};
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const auto FC = Register::AllocationOptions::FullyContiguous();
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SECTION(
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"Expect 0 + coexecSlots V_NOP(s) if VALU writes A after WMMA and A && B are *NOT* F8")
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{
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const auto v = t.createRegisters(Register::Type::Vector, DataType::Half, 5, 8, FC);
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// coexecSlots = 4, if first WMMA is not:
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// - v_wmma*_iu8; and
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// - v_wmma*_iu4; and
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// - v_wmma*f8f6f4 && A and B are not F8
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const auto expectedVNops = 0 + (coexecutionEnabled ? 4 : 0);
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std::vector<Instruction> insts
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= {Instruction("v_wmma_f16_16x16x32_f16", {v[0]}, {v[1], v[2], v[3]}, {}, ""),
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Instruction("v_add_f16",
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{v[1]->subset({0})},
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{v[4]->subset({1}), v[4]->subset({1})},
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{},
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""),
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Instruction("s_endpgm", {}, {}, {}, "")};
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t.peekAndSchedule(insts[0]);
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t.peekAndSchedule(insts[1], expectedVNops);
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CHECK(expectedVNops == countSubstring(t.output(), "v_nop"));
|
|
t.output().clear();
|
|
}
|
|
|
|
SECTION("Expect 0 + coexecSlots V_NOP(s) if VALU writes A after WMMA and A *IS* F8")
|
|
{
|
|
const auto [wmmaInst, types, regCounts] = GENERATE(
|
|
std::make_tuple(std::string{"v_wmma_f32_16x16x128_f8f6f4"},
|
|
std::make_tuple(DataType::Float, DataType::FP8x4, DataType::FP4x8),
|
|
std::make_tuple(8, 16, 8)),
|
|
std::make_tuple(std::string{"v_wmma_i32_16x16x64_iu8"},
|
|
std::make_tuple(DataType::Int32, DataType::Int32, DataType::Int32),
|
|
std::make_tuple(8, 8, 8)),
|
|
std::make_tuple(std::string{"v_wmma_f32_32x16x128_f4"},
|
|
std::make_tuple(DataType::Float, DataType::FP4x8, DataType::FP4x8),
|
|
std::make_tuple(16, 16, 8)));
|
|
|
|
if(wmmaInst == "v_wmma_f32_32x16x128_f4" && target.asicRevisionId != 1)
|
|
{
|
|
SKIP(fmt::format(
|
|
"Instruction {} is not supported on target {}\n", wmmaInst, toString(target)));
|
|
}
|
|
|
|
const auto [v0_dt, vA_dt, vB_dt] = types;
|
|
const auto [v0_count, vA_count, vB_count] = regCounts;
|
|
|
|
const auto v0 = t.createRegisters(Register::Type::Vector, v0_dt, 3, v0_count, FC);
|
|
const auto vA = t.createRegisters(Register::Type::Vector, vA_dt, 1, vA_count, FC);
|
|
const auto vB = t.createRegisters(Register::Type::Vector, vB_dt, 1, vB_count, FC);
|
|
// coexecSlots = 8, if first WMMA is:
|
|
// - v_wmma*_iu8; or
|
|
// - v_wmma*_iu4; or
|
|
// - v_wmma*f8f6f4 && A or B is F8
|
|
const auto expectedVNops = 0 + (coexecutionEnabled ? 8 : 0);
|
|
std::vector<Instruction> insts
|
|
= {Instruction(wmmaInst, {v0[0]}, {vA[0], vB[0], v0[1]}, {}, ""),
|
|
Instruction("v_add_f16",
|
|
{vA[0]->subset({1})},
|
|
{v0[2]->subset({1}), v0[2]->subset({1})},
|
|
{},
|
|
""),
|
|
Instruction("s_endpgm", {}, {}, {}, "")};
|
|
|
|
t.peekAndSchedule(insts[0]);
|
|
t.peekAndSchedule(insts[1], expectedVNops);
|
|
|
|
CHECK(expectedVNops == countSubstring(t.output(), "v_nop"));
|
|
t.output().clear();
|
|
}
|
|
|
|
SECTION("Expect 0 + coexecSlots V_NOP(s) if VALU writes D after WMMA and A && B "
|
|
"are *NOT* F8")
|
|
{
|
|
const auto v = t.createRegisters(Register::Type::Vector, DataType::Half, 5, 8, FC);
|
|
// coexecSlots = 4, if first WMMA is not:
|
|
// - v_wmma*_iu8; and
|
|
// - v_wmma*_iu4; and
|
|
// - v_wmma*f8f6f4 && A and B are not F8
|
|
const auto expectedVNops = 0 + (coexecutionEnabled ? 4 : 0);
|
|
std::vector<Instruction> insts
|
|
= {Instruction("v_wmma_f16_16x16x32_f16", {v[0]}, {v[1], v[2], v[3]}, {}, ""),
|
|
Instruction("v_add_f16",
|
|
{v[0]->subset({0})},
|
|
{v[4]->subset({1}), v[4]->subset({1})},
|
|
{},
|
|
""),
|
|
Instruction("s_endpgm", {}, {}, {}, "")};
|
|
|
|
t.peekAndSchedule(insts[0]);
|
|
t.peekAndSchedule(insts[1], expectedVNops);
|
|
|
|
CHECK(expectedVNops == countSubstring(t.output(), "v_nop"));
|
|
t.output().clear();
|
|
}
|
|
|
|
SECTION("Expect 0 + coexecSlots V_NOP(s) if VALU writes D after WMMA and A *IS* F8")
|
|
{
|
|
const auto [wmmaInst, types, regCounts] = GENERATE(
|
|
std::make_tuple(std::string{"v_wmma_f32_16x16x128_f8f6f4"},
|
|
std::make_tuple(DataType::Float, DataType::FP8x4, DataType::FP4x8),
|
|
std::make_tuple(8, 16, 8)),
|
|
std::make_tuple(std::string{"v_wmma_i32_16x16x64_iu8"},
|
|
std::make_tuple(DataType::Int32, DataType::Int32, DataType::Int32),
|
|
std::make_tuple(8, 8, 8)),
|
|
std::make_tuple(std::string{"v_wmma_f32_32x16x128_f4"},
|
|
std::make_tuple(DataType::Float, DataType::FP4x8, DataType::FP4x8),
|
|
std::make_tuple(16, 16, 8)));
|
|
|
|
if(wmmaInst == "v_wmma_f32_32x16x128_f4" && target.asicRevisionId != 1)
|
|
{
|
|
SKIP(fmt::format(
|
|
"Instruction {} is not supported on target {}\n", wmmaInst, toString(target)));
|
|
}
|
|
|
|
const auto [v0_dt, vA_dt, vB_dt] = types;
|
|
const auto [v0_count, vA_count, vB_count] = regCounts;
|
|
|
|
const auto v0 = t.createRegisters(Register::Type::Vector, v0_dt, 3, v0_count, FC);
|
|
const auto vA = t.createRegisters(Register::Type::Vector, vA_dt, 1, vA_count, FC);
|
|
const auto vB = t.createRegisters(Register::Type::Vector, vB_dt, 1, vB_count, FC);
|
|
// coexecSlots = 8, if first WMMA is:
|
|
// - v_wmma*_iu8; or
|
|
// - v_wmma*_iu4; or
|
|
// - v_wmma*f8f6f4 && A or B is F8
|
|
const auto expectedVNops = 0 + (coexecutionEnabled ? 8 : 0);
|
|
std::vector<Instruction> insts
|
|
= {Instruction(wmmaInst, {v0[0]}, {vA[0], vB[0], v0[1]}, {}, ""),
|
|
Instruction("v_add_f16",
|
|
{v0[0]->subset({0})},
|
|
{v0[2]->subset({1}), v0[2]->subset({1})},
|
|
{},
|
|
""),
|
|
Instruction("s_endpgm", {}, {}, {}, "")};
|
|
|
|
t.peekAndSchedule(insts[0]);
|
|
t.peekAndSchedule(insts[1], expectedVNops);
|
|
|
|
CHECK(expectedVNops == countSubstring(t.output(), "v_nop"));
|
|
t.output().clear();
|
|
}
|
|
}
|
|
}
|