derek.holloway
7502bf64a4
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766 lines
31 KiB
C++
766 lines
31 KiB
C++
/* ************************************************************************
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* Copyright (C) 2025-2026 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* ************************************************************************ */
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/**
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* @file GenLogicalIR.cpp
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* @brief Generates high-level IR instruction class definitions and builder methods
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*
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* This generator creates:
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* 1. IR instruction class definitions (LogicalInstructions_generated.hpp)
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* 2. Builder method forward declarations (StinkyBuilder_decls_generated.inc)
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* 3. Builder method implementations (StinkyBuilder_impls_generated.inc)
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* (Logical IR -> ASM mnemonic is per-arch via LogicalToAsmMappings_generated.inc from
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* GenLogicalToAsmMapping.cpp)
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*/
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#include <algorithm>
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#include <fstream>
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#include <iostream>
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#include <sstream>
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#include <string>
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#include <vector>
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namespace stinkytofu {
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// IR instruction definition (Logical IR has no mnemonics; ASM mnemonic is per-arch via
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// LogicalToAsmMappings)
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struct IRInstDef {
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std::string className; // e.g., "VAddF32"
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std::string comment; // e.g., "Vector add F32: dst = src0 + src1"
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int numSrcs; // Total number of source operands (required + optional)
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int numRequiredSrcs; // Number of required sources (rest are optional pointers)
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bool hasDest; // Whether it has a destination operand
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std::string category; // e.g., "Vector Arithmetic", "Scalar Bitwise"
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bool supportsDPP; // Whether this instruction supports DPP modifiers
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bool supportsSDWA; // Whether this instruction supports SDWA modifiers
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bool hasDS; // Whether this instruction has DS modifiers (for LDS operations)
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std::string flags; // Instruction flags (e.g., "IF_DSRead|IF_Commutative|IF_VALU")
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IRInstDef(const std::string& cls, const std::string& cmt, int srcs, bool dest = true,
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const std::string& cat = "", bool dpp = false, bool sdwa = false, bool ds = false,
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const std::string& flags = "",
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int reqSrcs = -1) // -1 means all sources are required (at end for backward compat)
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: className(cls),
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comment(cmt),
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numSrcs(srcs),
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numRequiredSrcs(reqSrcs == -1 ? srcs : reqSrcs),
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hasDest(dest),
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category(cat),
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supportsDPP(dpp),
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supportsSDWA(sdwa),
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hasDS(ds),
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flags(flags) {}
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};
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// Derive parse name (snake_case) from logical class name for getOpcodeMnemonic/parseOpcode.
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static std::string classNameToParseName(const std::string& className) {
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std::string out;
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out.reserve(className.size() + 4);
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for (size_t i = 0; i < className.size(); ++i) {
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char c = className[i];
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if (c >= 'A' && c <= 'Z') {
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if (i != 0) out += '_';
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out += char(c - 'A' + 'a');
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} else
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out += c;
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}
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return out;
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}
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// Define all high-level IR instructions
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// This is the "single source of truth" replacing manual class definitions
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// Instruction definitions are in a separate file for maintainability
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static std::vector<IRInstDef> getIRInstructions() {
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return {
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#include "../../src/ir/logical/LogicalInstructionDefs.inc"
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};
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}
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// Generate special instruction factory functions (pure enum design with specialData_)
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static bool genSpecialMFMAClasses(std::ofstream& out) {
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// Factory functions for special instructions (MFMA, Label, etc.)
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out << " // "
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"========================================================================\n";
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out << " // Special Instruction Factory Functions (Pure Enum Design)\n";
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out << " // "
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"========================================================================\n\n";
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out << " /**\n";
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out << " * @brief MFMA (Matrix Fused Multiply-Add) factory function\n";
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out << " * \n";
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out << " * Registers stored in: dests[0]=acc, srcs[0]=a, srcs[1]=b, srcs[2]=acc2 "
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"(optional)\n";
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out << " * Metadata stored in: specialData_ as MFMAData*\n";
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out << " */\n";
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out << " inline LogicalInstruction* MFMA(\n";
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out << " const std::string& instType,\n";
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out << " const std::string& accType,\n";
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out << " int m,\n";
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out << " int n,\n";
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out << " int k,\n";
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out << " int blocks,\n";
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out << " bool mfma1k,\n";
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out << " const StinkyRegister& acc,\n";
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out << " const StinkyRegister& a,\n";
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out << " const StinkyRegister& b,\n";
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out << " const StinkyRegister* acc2 = nullptr,\n";
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out << " bool neg = false,\n";
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out << " const std::string& matrixAFmt = \"\",\n";
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out << " const std::string& matrixBFmt = \"\",\n";
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out << " bool scaled = false,\n";
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out << " bool scaleOperands = false,\n";
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out << " const std::string& comment = \"\")\n";
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out << " {\n";
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out << " auto* inst = IRBase::createIR<LogicalInstruction>(logical::MFMA);\n";
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out << " \n";
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out << " // Populate registers\n";
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out << " inst->dests.push_back(acc);\n";
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out << " inst->srcs.push_back(a);\n";
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out << " inst->srcs.push_back(b);\n";
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out << " if (acc2) inst->srcs.push_back(*acc2);\n";
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out << " \n";
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out << " // Create and set special data\n";
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out << " auto* data = new MFMAData(instType, accType, m, n, k, blocks, mfma1k, "
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"neg, matrixAFmt, matrixBFmt, scaled, scaleOperands);\n";
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out << " inst->setSpecialData(data);\n";
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out << " inst->comment = comment;\n";
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out << " \n";
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out << " return inst;\n";
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out << " }\n\n";
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// MXMFMA factory
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out << " /**\n";
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out << " * @brief MXMFMA (MX format MFMA with scale factors) factory function\n";
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out << " * \n";
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out << " * Registers: dests[0]=acc, srcs[0]=a, srcs[1]=b, srcs[2]=acc2, srcs[3]=mxsa, "
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"srcs[4]=mxsb\n";
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out << " * Metadata stored in: specialData_ as MXMFMAData*\n";
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out << " */\n";
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out << " inline LogicalInstruction* MXMFMA(\n";
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out << " const std::string& instType,\n";
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out << " const std::string& accType,\n";
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out << " const std::string& mxScaleATypeStr,\n";
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out << " const std::string& mxScaleBTypeStr,\n";
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out << " int m,\n";
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out << " int n,\n";
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out << " int k,\n";
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out << " int block,\n";
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out << " const StinkyRegister& acc,\n";
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out << " const StinkyRegister& a,\n";
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out << " const StinkyRegister& b,\n";
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out << " const StinkyRegister& acc2,\n";
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out << " const StinkyRegister& mxsa,\n";
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out << " const StinkyRegister& mxsb,\n";
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out << " bool reuseA = false,\n";
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out << " bool reuseB = false,\n";
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out << " const std::string& matrixAFmt = \"\",\n";
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out << " const std::string& matrixBFmt = \"\",\n";
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out << " const std::string& comment = \"\")\n";
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out << " {\n";
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out << " auto* inst = IRBase::createIR<LogicalInstruction>(logical::MXMFMA);\n";
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out << " \n";
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out << " // Populate registers\n";
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out << " inst->dests.push_back(acc);\n";
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out << " inst->srcs.push_back(a);\n";
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out << " inst->srcs.push_back(b);\n";
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out << " inst->srcs.push_back(acc2);\n";
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out << " inst->srcs.push_back(mxsa);\n";
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out << " inst->srcs.push_back(mxsb);\n";
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out << " \n";
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out << " // Create and set special data\n";
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out << " auto* data = new MXMFMAData(instType, accType, mxScaleATypeStr, "
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"mxScaleBTypeStr,\n";
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out << " m, n, k, block, reuseA, reuseB, matrixAFmt, "
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"matrixBFmt);\n";
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out << " inst->setSpecialData(data);\n";
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out << " inst->comment = comment;\n";
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out << " \n";
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out << " return inst;\n";
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out << " }\n\n";
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// SMFMA factory
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out << " /**\n";
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out << " * @brief SMFMA (Sparse MFMA) factory function\n";
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out << " * \n";
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out << " * Registers: dests[0]=acc, srcs[0]=a, srcs[1]=b, srcs[2]=metadata\n";
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out << " * Metadata stored in: specialData_ as SMFMAData*\n";
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out << " */\n";
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out << " inline LogicalInstruction* SMFMA(\n";
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out << " const std::string& instType,\n";
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out << " const std::string& accType,\n";
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out << " int m,\n";
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out << " int n,\n";
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out << " int k,\n";
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out << " int blocks,\n";
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out << " bool mfma1k,\n";
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out << " const StinkyRegister& acc,\n";
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out << " const StinkyRegister& a,\n";
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out << " const StinkyRegister& b,\n";
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out << " const StinkyRegister& metadata,\n";
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out << " bool neg = false,\n";
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out << " const std::string& comment = \"\")\n";
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out << " {\n";
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out << " auto* inst = IRBase::createIR<LogicalInstruction>(logical::SMFMA);\n";
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out << " \n";
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out << " // Populate registers\n";
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out << " inst->dests.push_back(acc);\n";
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out << " inst->srcs.push_back(a);\n";
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out << " inst->srcs.push_back(b);\n";
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out << " inst->srcs.push_back(metadata);\n";
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out << " \n";
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out << " // Create and set special data\n";
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out << " auto* data = new SMFMAData(instType, accType, m, n, k, blocks, mfma1k, "
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"neg);\n";
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out << " inst->setSpecialData(data);\n";
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out << " inst->comment = comment;\n";
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out << " \n";
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out << " return inst;\n";
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out << " }\n\n";
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// Label factory
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out << " // "
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"========================================================================\n";
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out << " // Control Flow Instructions\n";
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out << " // "
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"========================================================================\n\n";
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out << " /**\n";
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out << " * @brief Label factory function for control flow\n";
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out << " * \n";
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out << " * Defines a label that can be used as a branch target.\n";
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out << " * Labels have no operands and do not produce output.\n";
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out << " * Metadata stored in: specialData_ as LogicalLabelData*\n";
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out << " */\n";
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out << " inline LogicalInstruction* Label(const std::string& labelName)\n";
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out << " {\n";
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out << " auto* inst = IRBase::createIR<LogicalInstruction>(logical::Label);\n";
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out << " \n";
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out << " // Labels have no operands\n";
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out << " \n";
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out << " // Create and set special data\n";
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out << " auto* data = new LogicalLabelData(labelName);\n";
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out << " inst->setSpecialData(data);\n";
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out << " \n";
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out << " return inst;\n";
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out << " }\n\n";
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return true;
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}
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// Generate IR instruction class definitions
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// Generate opcode enum values
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static bool genOpcodeEnum(const std::string& outdir) {
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std::ofstream out(outdir + "/LogicalOpcodes_generated.inc");
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if (!out) {
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std::cerr << "Failed to open LogicalOpcodes_generated.inc for writing\n";
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return false;
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}
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out << "// Auto-generated by TableGen - DO NOT EDIT\n";
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out << "// High-level IR opcode enumeration\n\n";
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int count = 0;
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// Generate opcode for each instruction
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for (const auto& inst : getIRInstructions()) {
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out << " " << inst.className << " = " << (count + 1) << ",\n";
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count++;
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}
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std::cout << "Generated " << count << " opcode enum values -> LogicalOpcodes_generated.inc\n";
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return true;
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}
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// Generate opcode to string mapping tables
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static bool genOpcodeMappings(const std::string& outdir) {
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std::ofstream out(outdir + "/stinkytofu/ir/logical/LogicalOpcode.cpp");
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if (!out) {
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std::cerr << "Failed to open LogicalOpcode.cpp for writing\n";
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return false;
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}
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// File header
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out << "/* ************************************************************************\n";
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out << " * Copyright (C) 2025-2026 Advanced Micro Devices, Inc.\n";
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out << " * AUTO-GENERATED FILE - DO NOT EDIT\n";
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out << " * Generated by: tools/tablegen/GenLogicalIR.cpp\n";
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out << " * ************************************************************************ */\n\n";
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out << "#include \"stinkytofu/ir/logical/LogicalOpcode.hpp\"\n\n";
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out << "namespace stinkytofu\n";
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out << "{\n";
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out << "namespace logical\n";
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out << "{\n\n";
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// Generate getOpcodeName function
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out << "const char* getOpcodeName(Opcode opcode)\n";
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out << "{\n";
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out << " switch (opcode)\n";
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out << " {\n";
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out << " case UNKNOWN:\n";
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out << " return \"UNKNOWN\";\n";
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for (const auto& inst : getIRInstructions()) {
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out << " case " << inst.className << ":\n";
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out << " return \"" << inst.className << "\";\n";
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}
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// Special opcodes (not auto-generated)
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out << " case MFMA:\n";
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out << " return \"MFMA\";\n";
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out << " case MXMFMA:\n";
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out << " return \"MXMFMA\";\n";
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out << " case SMFMA:\n";
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out << " return \"SMFMA\";\n";
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out << " case Label:\n";
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out << " return \"Label\";\n";
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out << " case IntrinsicCall:\n";
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out << " return \"IntrinsicCall\";\n";
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out << " case SWaitAlu:\n";
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out << " return \"SWaitAlu\";\n";
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out << " case SchedulingFence:\n";
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out << " return \"SchedulingFence\";\n";
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out << " default:\n";
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out << " return \"INVALID\";\n";
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out << " }\n";
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out << "}\n\n";
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// Generate getOpcodeMnemonic function
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out << "const char* getOpcodeMnemonic(Opcode opcode)\n";
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out << "{\n";
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out << " switch (opcode)\n";
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out << " {\n";
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out << " case UNKNOWN:\n";
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out << " return \"unknown\";\n";
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for (const auto& inst : getIRInstructions()) {
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out << " case " << inst.className << ":\n";
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out << " return \"" << classNameToParseName(inst.className) << "\";\n";
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}
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// Special opcodes (not auto-generated)
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out << " case MFMA:\n";
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out << " return \"mfma\";\n";
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out << " case MXMFMA:\n";
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out << " return \"mxmfma\";\n";
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out << " case SMFMA:\n";
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out << " return \"smfma\";\n";
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out << " case Label:\n";
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out << " return \"label\";\n";
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out << " case IntrinsicCall:\n";
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out << " return \"intrinsic_call\";\n";
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out << " case SWaitAlu:\n";
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out << " return \"s_wait_alu\";\n";
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out << " case SchedulingFence:\n";
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out << " return \"scheduling_fence\";\n";
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out << " default:\n";
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out << " return \"invalid\";\n";
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out << " }\n";
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out << "}\n\n";
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out << "} // namespace logical\n";
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out << "} // namespace stinkytofu\n";
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std::cout << "Generated opcode mapping functions -> LogicalOpcode.cpp\n";
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return true;
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}
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static bool genIRClasses(const std::string& outdir) {
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std::ofstream out(outdir + "/stinkytofu/ir/logical/LogicalInstructions_generated.hpp");
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if (!out) {
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std::cerr << "Failed to open LogicalInstructions_generated.hpp for writing\n";
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return false;
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}
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|
// File header with header guards
|
|
out << "/* ************************************************************************\n";
|
|
out << " * Copyright (C) 2025-2026 Advanced Micro Devices, Inc.\n";
|
|
out << " *\n";
|
|
out << " * Permission is hereby granted, free of charge, to any person obtaining a copy\n";
|
|
out << " * of this software and associated documentation files (the \"Software\"), to "
|
|
"deal\n";
|
|
out << " * in the Software without restriction, including without limitation the rights\n";
|
|
out << " * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n";
|
|
out << " * copies of the Software, and to permit persons to whom the Software is\n";
|
|
out << " * furnished to do so, subject to the following conditions:\n";
|
|
out << " *\n";
|
|
out << " * The above copyright notice and this permission notice shall be included in\n";
|
|
out << " * all copies or substantial portions of the Software.\n";
|
|
out << " *\n";
|
|
out << " * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n";
|
|
out << " * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n";
|
|
out << " * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n";
|
|
out << " * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n";
|
|
out << " * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n";
|
|
out << " * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n";
|
|
out << " * THE SOFTWARE.\n";
|
|
out << " *\n";
|
|
out << " * ************************************************************************ */\n\n";
|
|
out << "// Auto-generated by TableGen - DO NOT EDIT\n";
|
|
out << "// This file contains high-level IR instruction class definitions\n\n";
|
|
out << "#pragma once\n\n";
|
|
out << "#include \"stinkytofu/ir/asm/StinkyAsmIR.hpp\"\n";
|
|
out << "#include \"stinkytofu/ir/asm/StinkyModifiers.hpp\"\n";
|
|
out << "#include \"stinkytofu/core/stinkytofu.hpp\"\n";
|
|
out << "#include <iostream>\n";
|
|
out << "#include <optional>\n";
|
|
out << "#include <string>\n";
|
|
out << "\n// TODO: High-level IR should not depend on assembly-level IR "
|
|
"(StinkyAsmIR.hpp).\n";
|
|
out << "// Extract StinkyRegister and RegType into a separate header (e.g., "
|
|
"stinkytofu/ir/StinkyRegister.hpp)\n";
|
|
out << "// to fix the inverted dependency. StinkyRegister is a shared primitive used by "
|
|
"both\n";
|
|
out << "// high-level IR (LogicalInstruction) and assembly IR (StinkyInstruction).\n";
|
|
out << "#include <vector>\n\n";
|
|
out << "namespace stinkytofu\n";
|
|
out << "{\n\n";
|
|
out << " // NOTE: LogicalInstruction base class must be defined before including this "
|
|
"file\n\n";
|
|
|
|
std::string currentCategory = "";
|
|
for (const auto& inst : getIRInstructions()) {
|
|
if (inst.category != currentCategory) {
|
|
if (!currentCategory.empty()) {
|
|
out << "\n";
|
|
}
|
|
out << " // "
|
|
"========================================================================\n";
|
|
out << " // " << inst.category << "\n";
|
|
out << " // "
|
|
"========================================================================"
|
|
"\n\n";
|
|
currentCategory = inst.category;
|
|
}
|
|
|
|
// Generate factory function instead of subclass
|
|
out << " /**\n";
|
|
out << " * @brief Factory function for " << inst.comment << "\n";
|
|
out << " */\n";
|
|
out << " inline LogicalInstruction* " << inst.className << "(";
|
|
|
|
// Function parameters
|
|
if (inst.hasDest) {
|
|
out << "const StinkyRegister& dst";
|
|
if (inst.numSrcs > 0) out << ",\n" << std::string(inst.className.length() + 12, ' ');
|
|
}
|
|
|
|
for (int i = 0; i < inst.numSrcs; ++i) {
|
|
if (i > 0 || inst.hasDest) {
|
|
// Optional sources use pointer with default nullptr
|
|
if (i >= inst.numRequiredSrcs) {
|
|
out << "const StinkyRegister* src" << i << " = nullptr";
|
|
} else {
|
|
out << "const StinkyRegister& src" << i;
|
|
}
|
|
|
|
if (i < inst.numSrcs - 1)
|
|
out << ",\n" << std::string(inst.className.length() + 12, ' ');
|
|
} else {
|
|
// First source (no dest case)
|
|
if (i >= inst.numRequiredSrcs) {
|
|
out << "const StinkyRegister* src" << i << " = nullptr";
|
|
} else {
|
|
out << "const StinkyRegister& src" << i;
|
|
}
|
|
|
|
if (i < inst.numSrcs - 1)
|
|
out << ",\n" << std::string(inst.className.length() + 12, ' ');
|
|
}
|
|
}
|
|
|
|
if (inst.hasDest || inst.numSrcs > 0) {
|
|
out << ",\n" << std::string(inst.className.length() + 12, ' ');
|
|
}
|
|
|
|
// Add modifier parameters
|
|
if (inst.supportsDPP) {
|
|
out << "std::optional<DPPModifiers> dpp = std::nullopt,\n"
|
|
<< std::string(inst.className.length() + 12, ' ');
|
|
}
|
|
if (inst.supportsSDWA) {
|
|
out << "std::optional<SDWAModifiers> sdwa = std::nullopt,\n"
|
|
<< std::string(inst.className.length() + 12, ' ');
|
|
}
|
|
if (inst.hasDS) {
|
|
out << "std::optional<DSModifiers> ds = std::nullopt,\n"
|
|
<< std::string(inst.className.length() + 12, ' ');
|
|
}
|
|
|
|
out << "const std::string& comment = \"\")\n";
|
|
out << " {\n";
|
|
|
|
// Function body: create LogicalInstruction with opcode
|
|
out << " auto* inst = IRBase::createIR<LogicalInstruction>(logical::"
|
|
<< inst.className << ");\n";
|
|
|
|
// Set destinations
|
|
if (inst.hasDest) {
|
|
out << " inst->dests.push_back(dst);\n";
|
|
}
|
|
|
|
// Set sources (required and optional)
|
|
for (int i = 0; i < inst.numSrcs; ++i) {
|
|
if (i >= inst.numRequiredSrcs) {
|
|
// Optional source: check if pointer is non-null before adding
|
|
out << " if(src" << i << ") inst->srcs.push_back(*src" << i << ");\n";
|
|
} else {
|
|
// Required source: always add
|
|
out << " inst->srcs.push_back(src" << i << ");\n";
|
|
}
|
|
}
|
|
|
|
// Set modifiers
|
|
if (inst.supportsDPP) {
|
|
out << " inst->dpp = std::move(dpp);\n";
|
|
}
|
|
if (inst.supportsSDWA) {
|
|
out << " inst->sdwa = std::move(sdwa);\n";
|
|
}
|
|
if (inst.hasDS) {
|
|
out << " inst->ds = std::move(ds);\n";
|
|
}
|
|
|
|
// Set comment
|
|
out << " inst->comment = comment;\n";
|
|
|
|
// Set flags (parse from flags string)
|
|
if (!inst.flags.empty()) {
|
|
out << " // Set instruction flags\n";
|
|
out << " InstFlagSet flags;\n";
|
|
|
|
// Split flags by '|' and generate set() calls
|
|
std::string flagsStr = inst.flags;
|
|
size_t pos = 0;
|
|
while ((pos = flagsStr.find('|')) != std::string::npos) {
|
|
std::string flag = flagsStr.substr(0, pos);
|
|
// Trim whitespace
|
|
flag.erase(0, flag.find_first_not_of(" \t"));
|
|
flag.erase(flag.find_last_not_of(" \t") + 1);
|
|
if (!flag.empty()) {
|
|
out << " flags.set(" << flag << ");\n";
|
|
}
|
|
flagsStr.erase(0, pos + 1);
|
|
}
|
|
// Handle last flag
|
|
flagsStr.erase(0, flagsStr.find_first_not_of(" \t"));
|
|
flagsStr.erase(flagsStr.find_last_not_of(" \t") + 1);
|
|
if (!flagsStr.empty()) {
|
|
out << " flags.set(" << flagsStr << ");\n";
|
|
}
|
|
|
|
out << " inst->setFlags(flags);\n";
|
|
}
|
|
|
|
out << " return inst;\n";
|
|
out << " }\n\n";
|
|
}
|
|
|
|
// Generate special MFMA classes
|
|
genSpecialMFMAClasses(out);
|
|
|
|
// Generate helper implementations
|
|
out << "\n// "
|
|
"============================================================================\n";
|
|
out << "// Helper implementations (auto-generated)\n";
|
|
out << "// "
|
|
"============================================================================\n\n";
|
|
|
|
// Note: isCommutative() is now inline in LogicalInstructions.hpp using
|
|
// flags_.test(IF_Commutative)
|
|
|
|
// Generate isComposite() implementation
|
|
// Note: Composite instructions are determined by CompositeInstructionLoweringPass
|
|
out << "inline bool LogicalInstruction::isComposite() const\n";
|
|
out << "{\n";
|
|
out << " switch (opcode_) {\n";
|
|
out << " case logical::VAddPKF32:\n";
|
|
out << " case logical::VMulPKF32:\n";
|
|
out << " case logical::VMovB64:\n";
|
|
out << " case logical::VLShiftLeftOrB32:\n";
|
|
out << " case logical::SAddU64:\n";
|
|
out << " case logical::VAddNCU64:\n";
|
|
out << " case logical::VAddLShiftLeftU32:\n";
|
|
out << " case logical::VLShiftLeftAddU32:\n";
|
|
out << " return true;\n";
|
|
out << " default:\n";
|
|
out << " return false;\n";
|
|
out << " }\n";
|
|
out << "}\n\n";
|
|
|
|
// Close namespace
|
|
out << "} // namespace stinkytofu\n";
|
|
|
|
std::cout << "Generated " << getIRInstructions().size()
|
|
<< " LogicalInstruction factory functions + 5 special instruction factories "
|
|
"(MFMA/MXMFMA/SMFMA/Label/IntrinsicCall) -> "
|
|
"LogicalInstructions_generated.hpp\n";
|
|
return true;
|
|
}
|
|
|
|
// Generate builder method forward declarations
|
|
// Generate builder method implementations
|
|
// Generate C++ factory functions for all IR instructions
|
|
// Generate Python bindings for all IR instructions
|
|
static bool genPythonBindings(const std::string& outdir) {
|
|
std::ofstream out(outdir + "/PythonBindings_generated.inc");
|
|
if (!out) {
|
|
std::cerr << "Failed to open PythonBindings_generated.inc for writing\n";
|
|
return false;
|
|
}
|
|
|
|
out << "// Auto-generated Python bindings for IR instructions\n";
|
|
out << "// DO NOT EDIT - Generated by GenLogicalIR.cpp\n\n";
|
|
|
|
int count = 0;
|
|
|
|
// Generate bindings for all regular IR instructions
|
|
for (const auto& inst : getIRInstructions()) {
|
|
std::string className = inst.className;
|
|
|
|
// Generate factory function instead of constructor
|
|
out << " m.def(\"" << className << "\", [](";
|
|
|
|
// Constructor parameter types
|
|
std::vector<std::string> paramTypes;
|
|
std::vector<std::string> paramNames;
|
|
std::vector<std::string> defaults;
|
|
|
|
// Add destination register (if instruction has one)
|
|
if (inst.hasDest) {
|
|
paramTypes.push_back("const StinkyRegister&");
|
|
paramNames.push_back("dest");
|
|
defaults.push_back("");
|
|
}
|
|
|
|
// Add source operands (required and optional)
|
|
for (int i = 0; i < inst.numSrcs; i++) {
|
|
if (i >= inst.numRequiredSrcs) {
|
|
// Optional source: use std::optional wrapper for Python
|
|
paramTypes.push_back("std::optional<StinkyRegister>");
|
|
paramNames.push_back("src" + std::to_string(i));
|
|
defaults.push_back("std::nullopt");
|
|
} else {
|
|
// Required source: regular reference
|
|
paramTypes.push_back("const StinkyRegister&");
|
|
paramNames.push_back("src" + std::to_string(i));
|
|
defaults.push_back("");
|
|
}
|
|
}
|
|
|
|
// Add optional modifiers
|
|
if (inst.supportsDPP && inst.supportsSDWA) {
|
|
paramTypes.push_back("std::optional<DPPModifiers>");
|
|
paramNames.push_back("dpp");
|
|
defaults.push_back("std::nullopt");
|
|
|
|
paramTypes.push_back("std::optional<SDWAModifiers>");
|
|
paramNames.push_back("sdwa");
|
|
defaults.push_back("std::nullopt");
|
|
} else if (inst.hasDS) {
|
|
paramTypes.push_back("std::optional<DSModifiers>");
|
|
paramNames.push_back("ds");
|
|
defaults.push_back("std::nullopt");
|
|
}
|
|
|
|
// Add comment parameter
|
|
paramTypes.push_back("const std::string&");
|
|
paramNames.push_back("comment");
|
|
defaults.push_back("\"\"");
|
|
|
|
// Output lambda parameter list
|
|
for (size_t i = 0; i < paramTypes.size(); i++) {
|
|
out << paramTypes[i] << " " << paramNames[i];
|
|
if (i + 1 < paramTypes.size()) out << ", ";
|
|
}
|
|
out << ") {\n";
|
|
|
|
// Return factory function wrapped in shared_ptr (Python-owned: set ownedExternally)
|
|
out << " return makeLogicalInstructionShared(" << className << "(";
|
|
|
|
// Pass parameters, converting optional sources to pointers
|
|
for (size_t i = 0; i < paramNames.size(); i++) {
|
|
const std::string& paramName = paramNames[i];
|
|
|
|
// Check if this is an optional source parameter
|
|
bool isOptionalSrc = paramName.starts_with("src") &&
|
|
paramTypes[i].find("std::optional") != std::string::npos;
|
|
|
|
if (isOptionalSrc) {
|
|
// Convert std::optional<StinkyRegister> to const StinkyRegister*
|
|
out << "(" << paramName << ".has_value() ? &" << paramName << ".value() : nullptr)";
|
|
} else {
|
|
// Regular parameter: pass as-is
|
|
out << paramName;
|
|
}
|
|
|
|
if (i + 1 < paramNames.size()) out << ", ";
|
|
}
|
|
out << "));\n";
|
|
out << " },\n";
|
|
|
|
// Output parameter names and defaults
|
|
for (size_t i = 0; i < paramNames.size(); i++) {
|
|
out << " nb::arg(\"" << paramNames[i] << "\")";
|
|
if (!defaults[i].empty()) out << " = " << defaults[i];
|
|
if (i + 1 < paramNames.size()) out << ",\n";
|
|
}
|
|
out << ",\n";
|
|
|
|
// Add docstring
|
|
out << " \"Create a " << classNameToParseName(inst.className) << " instruction\");\n\n";
|
|
count++;
|
|
}
|
|
|
|
std::cout << "Generated Python bindings for " << count
|
|
<< " IR instructions -> PythonBindings_generated.inc\n";
|
|
return true;
|
|
}
|
|
|
|
// Generate all high-level IR artifacts
|
|
// NOLINTNEXTLINE(misc-use-internal-linkage)
|
|
bool genLogicalIR(const std::string& outdir) {
|
|
bool success = true;
|
|
|
|
std::cout << "\n=== Generating High-Level IR ===\n";
|
|
|
|
success &= genOpcodeEnum(outdir);
|
|
success &= genOpcodeMappings(outdir);
|
|
success &= genIRClasses(outdir);
|
|
// Obsolete: genBuilderDecls, genBuilderImpls, genFactoryFunctions
|
|
// These are replaced by inline factory functions in LogicalInstructions_generated.hpp
|
|
success &= genPythonBindings(outdir);
|
|
|
|
if (success) {
|
|
std::cout << "=== High-Level IR generation completed successfully ===\n\n";
|
|
} else {
|
|
std::cerr << "=== High-Level IR generation failed ===\n\n";
|
|
}
|
|
|
|
return success;
|
|
}
|
|
|
|
} // namespace stinkytofu
|