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104 lines
4.1 KiB
C++
104 lines
4.1 KiB
C++
// Semantics for 32-bit Motorola-IBM PowerPC microprocessors using ROSE instruction semantics API2
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// This code was derived from $ROSE/projects/assemblyToSourceAst/powerpcInstructionSemantics.h,
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// which is mostly a copy of $ROSE/projects/SemanticSignatureVectors/powerpcInstructionSemantics.h
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//
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// The ROSE style guide indicates that PowerPC, when used as part of a symbol in ROSE source code,
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// should be capitalized as "Powerpc" (e.g., "DispatcherPowerpc", the same rule that consistently
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// capitializes x86 as "DispatcherX86").
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#ifndef ROSE_DispatcherPpc_H
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#define ROSE_DispatcherPpc_H
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#include <assert.h>
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#include <stddef.h>
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#include "BaseSemantics2.h"
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#include "../SgAsmPowerpcInstruction.h"
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#include "external/rose/powerpcInstructionEnum.h"
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namespace rose {
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namespace BinaryAnalysis {
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namespace InstructionSemantics2 {
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/** Shared-ownership pointer to a PowerPC instruction dispatcher. See @ref heap_object_shared_ownership. */
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typedef dyncompat::shared_ptr<class DispatcherPowerpc> DispatcherPowerpcPtr;
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class DispatcherPowerpc: public BaseSemantics::Dispatcher {
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protected:
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// prototypical constructor
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DispatcherPowerpc(): BaseSemantics::Dispatcher(32, RegisterDictionary::dictionary_powerpc()) {}
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DispatcherPowerpc(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
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: BaseSemantics::Dispatcher(ops, addrWidth, regs ? regs : RegisterDictionary::dictionary_powerpc()) {
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// ASSERT_require(32==addrWidth);
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regcache_init();
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iproc_init();
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memory_init();
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}
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/** Loads the iproc table with instruction processing functors. This normally happens from the constructor. */
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void iproc_init();
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/** Load the cached register descriptors. This happens at construction and on set_register_dictionary() calls. */
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void regcache_init();
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/** Make sure memory is set up correctly. For instance, byte order should be little endian. */
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void memory_init();
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public:
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/** Cached register. This register is cached so that there are not so many calls to Dispatcher::findRegister(). The
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* register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).
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* @{ */
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RegisterDescriptor REG_IAR, REG_LR, REG_XER, REG_CR, REG_CR0, REG_CTR;
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/** @}*/
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/** Construct a prototypical dispatcher. The only thing this dispatcher can be used for is to create another dispatcher
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* with the virtual @ref create method. */
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static DispatcherPowerpcPtr instance() {
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return DispatcherPowerpcPtr(new DispatcherPowerpc);
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}
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/** Constructor. */
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static DispatcherPowerpcPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth,
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const RegisterDictionary *regs=NULL) {
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return DispatcherPowerpcPtr(new DispatcherPowerpc(ops, addrWidth, regs));
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}
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/** Virtual constructor. */
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virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0,
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const RegisterDictionary *regs=NULL) const {
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if (0==addrWidth)
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addrWidth = addressWidth();
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if (!regs)
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regs = get_register_dictionary();
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return instance(ops, addrWidth, regs);
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}
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/** Dynamic cast to a DispatcherPowerpcPtr with assertion. */
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static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &d) {
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DispatcherPowerpcPtr retval = dyncompat::dynamic_pointer_cast<DispatcherPowerpc>(d);
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assert(retval!=NULL);
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return retval;
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}
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virtual void set_register_dictionary(const RegisterDictionary *regdict) ;
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virtual RegisterDescriptor instructionPointerRegister() const ;
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virtual RegisterDescriptor stackPointerRegister() const ;
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virtual int iproc_key(SgAsmInstruction *insn_) const {
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SgAsmPowerpcInstruction *insn = isSgAsmPowerpcInstruction(insn_);
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assert(insn!=NULL);
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return insn->get_kind();
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}
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/** Write status flags for result. */
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virtual void record(const BaseSemantics::SValuePtr &result);
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};
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} // namespace
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} // namespace
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} // namespace
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#endif
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