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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

468 lines
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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX950,GFX950-SDAG %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX950,GFX950-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-SDAG,GFX1250-TRUE16,GFX1250-SDG-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-SDAG,GFX1250-FAKE16,GFX1250-SDG-FAKE16 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-TRUE16,GFX1250-GISEL-TRUE16 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1250,GFX1250-GISEL,GFX1250-FAKE16,GFX1250-GISEL-FAKE16 %s
declare i32 @llvm.amdgcn.bitop3.i32(i32, i32, i32, i32)
declare i16 @llvm.amdgcn.bitop3.i16(i16, i16, i16, i32)
define amdgpu_ps float @bitop3_b32_vvv(i32 %a, i32 %b, i32 %c) {
; GFX950-LABEL: bitop3_b32_vvv:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xf
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: bitop3_b32_vvv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0xf
; GFX1250-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 15)
%ret_cast = bitcast i32 %ret to float
ret float %ret_cast
}
define amdgpu_ps float @bitop3_b32_svv(i32 inreg %a, i32 %b, i32 %c) {
; GFX950-LABEL: bitop3_b32_svv:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x10
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: bitop3_b32_svv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x10
; GFX1250-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 16)
%ret_cast = bitcast i32 %ret to float
ret float %ret_cast
}
define amdgpu_ps float @bitop3_b32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {
; GFX950-LABEL: bitop3_b32_ssv:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_mov_b32_e32 v1, s1
; GFX950-NEXT: v_bitop3_b32 v0, s0, v1, v0 bitop3:0x11
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: bitop3_b32_ssv:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: v_bitop3_b32 v0, s0, s1, v0 bitop3:0x11
; GFX1250-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 17)
%ret_cast = bitcast i32 %ret to float
ret float %ret_cast
}
define amdgpu_ps float @bitop3_b32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
; GFX950-LABEL: bitop3_b32_sss:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_mov_b32_e32 v0, s1
; GFX950-NEXT: v_mov_b32_e32 v1, s2
; GFX950-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x12
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: bitop3_b32_sss:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-NEXT: v_bitop3_b32 v0, s0, s1, v0 bitop3:0x12
; GFX1250-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 %c, i32 18)
%ret_cast = bitcast i32 %ret to float
ret float %ret_cast
}
define amdgpu_ps float @bitop3_b32_vvi(i32 %a, i32 %b) {
; GFX950-SDAG-LABEL: bitop3_b32_vvi:
; GFX950-SDAG: ; %bb.0:
; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x3e8
; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, v1, s0 bitop3:0x13
; GFX950-SDAG-NEXT: ; return to shader part epilog
;
; GFX950-GISEL-LABEL: bitop3_b32_vvi:
; GFX950-GISEL: ; %bb.0:
; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8
; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x13
; GFX950-GISEL-NEXT: ; return to shader part epilog
;
; GFX1250-LABEL: bitop3_b32_vvi:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: v_bitop3_b32 v0, v0, v1, 0x3e8 bitop3:0x13
; GFX1250-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 %b, i32 1000, i32 19)
%ret_cast = bitcast i32 %ret to float
ret float %ret_cast
}
define amdgpu_ps float @bitop3_b32_vii(i32 %a) {
; GFX950-SDAG-LABEL: bitop3_b32_vii:
; GFX950-SDAG: ; %bb.0:
; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x7d0
; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX950-SDAG-NEXT: v_bitop3_b32 v0, v0, s0, v1 bitop3:0x14
; GFX950-SDAG-NEXT: ; return to shader part epilog
;
; GFX950-GISEL-LABEL: bitop3_b32_vii:
; GFX950-GISEL: ; %bb.0:
; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, 0x7d0
; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8
; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x14
; GFX950-GISEL-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-LABEL: bitop3_b32_vii:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_nop
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT: s_movk_i32 s0, 0x7d0
; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, v0, s0, 0x3e8 bitop3:0x14
; GFX1250-SDAG-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: bitop3_b32_vii:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT: v_nop
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, v0, 0x7d0, v1 bitop3:0x14
; GFX1250-GISEL-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 %a, i32 2000, i32 1000, i32 20)
%ret_cast = bitcast i32 %ret to float
ret float %ret_cast
}
; FIXME: Constant fold this
define amdgpu_ps float @bitop3_b32_iii() {
; GFX950-SDAG-LABEL: bitop3_b32_iii:
; GFX950-SDAG: ; %bb.0:
; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xbb8
; GFX950-SDAG-NEXT: v_mov_b32_e32 v0, 0x7d0
; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX950-SDAG-NEXT: v_bitop3_b32 v0, s0, v0, v1 bitop3:0x15
; GFX950-SDAG-NEXT: ; return to shader part epilog
;
; GFX950-GISEL-LABEL: bitop3_b32_iii:
; GFX950-GISEL: ; %bb.0:
; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, 0xbb8
; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, 0x7d0
; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8
; GFX950-GISEL-NEXT: v_bitop3_b32 v0, v0, v1, v2 bitop3:0x15
; GFX950-GISEL-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-LABEL: bitop3_b32_iii:
; GFX1250-SDAG: ; %bb.0:
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDAG-NEXT: v_nop
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0x3e8
; GFX1250-SDAG-NEXT: s_movk_i32 s0, 0xbb8
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-NEXT: v_bitop3_b32 v0, s0, 0x7d0, v0 bitop3:0x15
; GFX1250-SDAG-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-LABEL: bitop3_b32_iii:
; GFX1250-GISEL: ; %bb.0:
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-NEXT: v_nop
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0x7d0
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_bitop3_b32 v0, 0xbb8, v0, v1 bitop3:0x15
; GFX1250-GISEL-NEXT: ; return to shader part epilog
%ret = call i32 @llvm.amdgcn.bitop3.i32(i32 3000, i32 2000, i32 1000, i32 21)
%ret_cast = bitcast i32 %ret to float
ret float %ret_cast
}
define amdgpu_ps half @bitop3_b16_vvv(i16 %a, i16 %b, i16 %c) {
; GFX950-LABEL: bitop3_b16_vvv:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0xf
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-TRUE16-LABEL: bitop3_b16_vvv:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-TRUE16-NEXT: v_nop
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, v2.l bitop3:0xf
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_vvv:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-FAKE16-NEXT: v_nop
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0xf
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 15)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
}
define amdgpu_ps half @bitop3_b16_svv(i16 inreg %a, i16 %b, i16 %c) {
; GFX950-LABEL: bitop3_b16_svv:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x10
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-TRUE16-LABEL: bitop3_b16_svv:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-TRUE16-NEXT: v_nop
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, v0.l, v1.l bitop3:0x10
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_svv:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-FAKE16-NEXT: v_nop
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x10
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 16)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
}
define amdgpu_ps half @bitop3_b16_ssv(i16 inreg %a, i16 inreg %b, i16 %c) {
; GFX950-LABEL: bitop3_b16_ssv:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_mov_b32_e32 v1, s1
; GFX950-NEXT: v_bitop3_b16 v0, s0, v1, v0 bitop3:0x11
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-TRUE16-LABEL: bitop3_b16_ssv:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-TRUE16-NEXT: v_nop
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x11
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_ssv:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-FAKE16-NEXT: v_nop
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, s1, v0 bitop3:0x11
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 17)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
}
define amdgpu_ps half @bitop3_b16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c) {
; GFX950-LABEL: bitop3_b16_sss:
; GFX950: ; %bb.0:
; GFX950-NEXT: v_mov_b32_e32 v0, s1
; GFX950-NEXT: v_mov_b32_e32 v1, s2
; GFX950-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x12
; GFX950-NEXT: ; return to shader part epilog
;
; GFX1250-TRUE16-LABEL: bitop3_b16_sss:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-TRUE16-NEXT: v_nop
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_sss:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-FAKE16-NEXT: v_nop
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, s0, s1, v0 bitop3:0x12
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 %c, i32 18)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
}
define amdgpu_ps half @bitop3_b16_vvi(i16 %a, i16 %b) {
; GFX950-SDAG-LABEL: bitop3_b16_vvi:
; GFX950-SDAG: ; %bb.0:
; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x3e8
; GFX950-SDAG-NEXT: v_bitop3_b16 v0, v0, v1, s0 bitop3:0x13
; GFX950-SDAG-NEXT: ; return to shader part epilog
;
; GFX950-GISEL-LABEL: bitop3_b16_vvi:
; GFX950-GISEL: ; %bb.0:
; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8
; GFX950-GISEL-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0x13
; GFX950-GISEL-NEXT: ; return to shader part epilog
;
; GFX1250-TRUE16-LABEL: bitop3_b16_vvi:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-TRUE16-NEXT: v_nop
; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0x3e8 bitop3:0x13
; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_vvi:
; GFX1250-FAKE16: ; %bb.0:
; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-FAKE16-NEXT: v_nop
; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v0, v0, v1, 0x3e8 bitop3:0x13
; GFX1250-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 %b, i16 1000, i32 19)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
}
define amdgpu_ps half @bitop3_b16_vii(i16 %a) {
; GFX950-SDAG-LABEL: bitop3_b16_vii:
; GFX950-SDAG: ; %bb.0:
; GFX950-SDAG-NEXT: s_movk_i32 s0, 0x7d0
; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX950-SDAG-NEXT: v_bitop3_b16 v0, v0, s0, v1 bitop3:0x14
; GFX950-SDAG-NEXT: ; return to shader part epilog
;
; GFX950-GISEL-LABEL: bitop3_b16_vii:
; GFX950-GISEL: ; %bb.0:
; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, 0x7d0
; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8
; GFX950-GISEL-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0x14
; GFX950-GISEL-NEXT: ; return to shader part epilog
;
; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_vii:
; GFX1250-SDG-TRUE16: ; %bb.0:
; GFX1250-SDG-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDG-TRUE16-NEXT: v_nop
; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x7d0
; GFX1250-SDG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v1.l, 0x3e8 bitop3:0x14
; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-SDG-FAKE16-LABEL: bitop3_b16_vii:
; GFX1250-SDG-FAKE16: ; %bb.0:
; GFX1250-SDG-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDG-FAKE16-NEXT: v_nop
; GFX1250-SDG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDG-FAKE16-NEXT: s_movk_i32 s0, 0x7d0
; GFX1250-SDG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDG-FAKE16-NEXT: v_bitop3_b16 v0, v0, s0, 0x3e8 bitop3:0x14
; GFX1250-SDG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_vii:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-TRUE16-NEXT: v_nop
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x3e8
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, 0x7d0, v0.h bitop3:0x14
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: bitop3_b16_vii:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT: v_nop
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, v0, 0x7d0, v1 bitop3:0x14
; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 %a, i16 2000, i16 1000, i32 20)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
}
; FIXME: Constant fold this
define amdgpu_ps half @bitop3_b16_iii() {
; GFX950-SDAG-LABEL: bitop3_b16_iii:
; GFX950-SDAG: ; %bb.0:
; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xbb8
; GFX950-SDAG-NEXT: v_mov_b32_e32 v0, 0x7d0
; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX950-SDAG-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x15
; GFX950-SDAG-NEXT: ; return to shader part epilog
;
; GFX950-GISEL-LABEL: bitop3_b16_iii:
; GFX950-GISEL: ; %bb.0:
; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, 0xbb8
; GFX950-GISEL-NEXT: v_mov_b32_e32 v1, 0x7d0
; GFX950-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e8
; GFX950-GISEL-NEXT: v_bitop3_b16 v0, v0, v1, v2 bitop3:0x15
; GFX950-GISEL-NEXT: ; return to shader part epilog
;
; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_iii:
; GFX1250-SDG-TRUE16: ; %bb.0:
; GFX1250-SDG-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDG-TRUE16-NEXT: v_nop
; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7d0
; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0xbb8
; GFX1250-SDG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.h, v0.l, 0x3e8 bitop3:0x15
; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-SDG-FAKE16-LABEL: bitop3_b16_iii:
; GFX1250-SDG-FAKE16: ; %bb.0:
; GFX1250-SDG-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-SDG-FAKE16-NEXT: v_nop
; GFX1250-SDG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-SDG-FAKE16-NEXT: v_mov_b32_e32 v0, 0x3e8
; GFX1250-SDG-FAKE16-NEXT: s_movk_i32 s0, 0xbb8
; GFX1250-SDG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1250-SDG-FAKE16-NEXT: v_bitop3_b16 v0, s0, 0x7d0, v0 bitop3:0x15
; GFX1250-SDG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-TRUE16-LABEL: bitop3_b16_iii:
; GFX1250-GISEL-TRUE16: ; %bb.0:
; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-TRUE16-NEXT: v_nop
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7d0
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x3e8
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, 0xbb8, v0.l, v0.h bitop3:0x15
; GFX1250-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: bitop3_b16_iii:
; GFX1250-GISEL-FAKE16: ; %bb.0:
; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT: v_nop
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7d0
; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0x3e8
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-FAKE16-NEXT: v_bitop3_b16 v0, 0xbb8, v0, v1 bitop3:0x15
; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
%ret = call i16 @llvm.amdgcn.bitop3.i16(i16 3000, i16 2000, i16 1000, i32 21)
%ret_cast = bitcast i16 %ret to half
ret half %ret_cast
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}
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