derek.holloway
7502bf64a4
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363 lines
14 KiB
LLVM
363 lines
14 KiB
LLVM
; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=ppc64le-- -mcpu=pwr8 | FileCheck %s --check-prefixes=CHECK,CHECK-P8
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; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=ppc64le-- -mcpu=pwr9 | FileCheck %s --check-prefixes=CHECK,CHECK-P9
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define <16 x i8> @test1_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test1_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
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define <16 x i8> @test2_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test2_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vaddubm v[[REG3:[0-9]+]], v2, v[[REG2]]
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define <16 x i8> @test3_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test3_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v[[REG2]], v2
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; negtive constant
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define <16 x i8> @test4_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test4_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],
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; CHECK-NEXT: vsububm v[[REG4:[0-9]+]], v[[REG2]], v[[REG3]]
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define <16 x i8> @test5_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test5_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vaddubm v[[REG4:[0-9]+]], v2, v[[REG3]]
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; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],
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; CHECK-NEXT: vsububm v[[REG5:[0-9]+]], v[[REG2]], v[[REG4]]
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define <16 x i8> @test6_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test6_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 4
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v2, v[[REG2]]
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; boundary case
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define <16 x i8> @test7_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test7_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 7
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 7
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]]
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define <16 x i8> @test8_v16i8(<16 x i8> %a) {
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%tmp.1 = mul nsw <16 x i8> %a, <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127> ; <<16 x i8>> [#uses=1]
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ret <16 x i8> %tmp.1
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}
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; CHECK-LABEL: test8_v16i8:
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; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 7
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; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 7
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v[[REG2]], v2
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define <8 x i16> @test1_v8i16(<8 x i16> %a) {
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%tmp.1 = mul nsw <8 x i16> %a, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16> ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp.1
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}
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; CHECK-LABEL: test1_v8i16:
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; CHECK: vspltish v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
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define <8 x i16> @test2_v8i16(<8 x i16> %a) {
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%tmp.1 = mul nsw <8 x i16> %a, <i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17> ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp.1
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}
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; CHECK-LABEL: test2_v8i16:
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; CHECK: vspltish v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vadduhm v[[REG3:[0-9]+]], v2, v[[REG2]]
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define <8 x i16> @test3_v8i16(<8 x i16> %a) {
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%tmp.1 = mul nsw <8 x i16> %a, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp.1
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}
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; CHECK-LABEL: test3_v8i16:
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; CHECK: vspltish v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v[[REG2]], v2
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; negtive constant
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define <8 x i16> @test4_v8i16(<8 x i16> %a) {
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%tmp.1 = mul nsw <8 x i16> %a, <i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16> ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp.1
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}
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; CHECK-LABEL: test4_v8i16:
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; CHECK: vspltish v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],
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; CHECK-NEXT: vsubuhm v[[REG4:[0-9]+]], v[[REG2]], v[[REG3]]
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define <8 x i16> @test5_v8i16(<8 x i16> %a) {
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%tmp.1 = mul nsw <8 x i16> %a, <i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17> ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp.1
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}
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; CHECK-LABEL: test5_v8i16:
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; CHECK: vspltish v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vadduhm v[[REG4:[0-9]+]], v2, v[[REG3]]
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; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],
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; CHECK-NEXT: vsubuhm v[[REG5:[0-9]+]], v[[REG2]], v[[REG4]]
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define <8 x i16> @test6_v8i16(<8 x i16> %a) {
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%tmp.1 = mul nsw <8 x i16> %a, <i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15> ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp.1
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}
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; CHECK-LABEL: test6_v8i16:
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; CHECK: vspltish v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v2, v[[REG2]]
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; boundary case
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define <8 x i16> @test7_v8i16(<8 x i16> %a) {
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%tmp.1 = mul nsw <8 x i16> %a, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768> ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp.1
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}
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; CHECK-LABEL: test7_v8i16:
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; CHECK: vspltish v[[REG1:[0-9]+]], 15
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]
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define <8 x i16> @test8_v8i16(<8 x i16> %a) {
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%tmp.1 = mul nsw <8 x i16> %a, <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767> ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %tmp.1
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}
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; CHECK-LABEL: test8_v8i16:
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; CHECK: vspltish v[[REG1:[0-9]+]], 15
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v[[REG2]], v2
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define <4 x i32> @test1_v4i32(<4 x i32> %a) {
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%tmp.1 = mul nsw <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp.1
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}
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; CHECK-LABEL: test1_v4i32:
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; CHECK: vspltisw v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
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define <4 x i32> @test2_v4i32(<4 x i32> %a) {
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%tmp.1 = mul nsw <4 x i32> %a, <i32 17, i32 17, i32 17, i32 17> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp.1
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}
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; CHECK-LABEL: test2_v4i32:
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; CHECK: vspltisw v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vadduwm v[[REG3:[0-9]+]], v2, v[[REG2]]
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define <4 x i32> @test3_v4i32(<4 x i32> %a) {
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%tmp.1 = mul nsw <4 x i32> %a, <i32 15, i32 15, i32 15, i32 15> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp.1
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}
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; CHECK-LABEL: test3_v4i32:
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; CHECK: vspltisw v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsubuwm v[[REG3:[0-9]+]], v[[REG2]], v2
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; negtive constant
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define <4 x i32> @test4_v4i32(<4 x i32> %a) {
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%tmp.1 = mul nsw <4 x i32> %a, <i32 -16, i32 -16, i32 -16, i32 -16> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp.1
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}
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; CHECK-LABEL: test4_v4i32:
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; CHECK: vspltisw v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-P8-NEXT: xxlxor v[[REG3:[0-9]+]],
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; CHECK-P8-NEXT: vsubuwm v{{[0-9]+}}, v[[REG3]], v[[REG2]]
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; CHECK-P9-NEXT: vnegw v{{[0-9]+}}, v[[REG2]]
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define <4 x i32> @test5_v4i32(<4 x i32> %a) {
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%tmp.1 = mul nsw <4 x i32> %a, <i32 -17, i32 -17, i32 -17, i32 -17> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp.1
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}
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; CHECK-LABEL: test5_v4i32:
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; CHECK: vspltisw v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vadduwm v[[REG3:[0-9]+]], v2, v[[REG2]]
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; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]],
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; CHECK-P8-NEXT: vsubuwm v{{[0-9]+}}, v[[REG4]], v[[REG3]]
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; CHECK-P9-NEXT: vnegw v{{[0-9]+}}, v[[REG3]]
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define <4 x i32> @test6_v4i32(<4 x i32> %a) {
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%tmp.1 = mul nsw <4 x i32> %a, <i32 -15, i32 -15, i32 -15, i32 -15> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp.1
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}
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; CHECK-LABEL: test6_v4i32:
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; CHECK: vspltisw v[[REG1:[0-9]+]], 4
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]
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; CHECK-NEXT: vsubuwm v[[REG3:[0-9]+]], v2, v[[REG2]]
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; boundary case
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define <4 x i32> @test7_v4i32(<4 x i32> %a) {
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%tmp.1 = mul nsw <4 x i32> %a, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp.1
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}
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; CHECK-LABEL: test7_v4i32:
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; CHECK: xxleqv v[[REG1:[0-9]+]], v[[REG2:[0-9]+]], v[[REG2]]
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; CHECK-NOT: vmul
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; CHECK-NEXT: vslw v[[REG3:[0-9]+]], v2, v[[REG1]]
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define <4 x i32> @test8_v4i32(<4 x i32> %a) {
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%tmp.1 = mul nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp.1
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}
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; CHECK-LABEL: test8_v4i32:
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; CHECK: xxleqv v[[REG1:[0-9]+]], v[[REG2:[0-9]+]], v[[REG2]]
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; CHECK-NOT: vmul
|
|
; CHECK-NEXT: vslw v[[REG3:[0-9]+]], v2, v[[REG1]]
|
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; CHECK-NEXT: vsubuwm v[[REG4:[0-9]+]], v[[REG3]], v2
|
|
|
|
define <2 x i64> @test1_v2i64(<2 x i64> %a) {
|
|
%tmp.1 = mul nsw <2 x i64> %a, <i64 16, i64 16> ; <<2 x i64>> [#uses=1]
|
|
ret <2 x i64> %tmp.1
|
|
}
|
|
; CHECK-LABEL: test1_v2i64:
|
|
; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}
|
|
; CHECK-NOT: vmul
|
|
; CHECK-NEXT: vsld v{{[0-9]+}}, v2, v[[REG2]]
|
|
|
|
define <2 x i64> @test2_v2i64(<2 x i64> %a) {
|
|
%tmp.1 = mul nsw <2 x i64> %a, <i64 17, i64 17> ; <<2 x i64>> [#uses=1]
|
|
ret <2 x i64> %tmp.1
|
|
}
|
|
|
|
; CHECK-LABEL: test2_v2i64:
|
|
; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}
|
|
; CHECK-NOT: vmul
|
|
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
|
; CHECK-NEXT: vaddudm v{{[0-9]+}}, v2, v[[REG3]]
|
|
|
|
define <2 x i64> @test3_v2i64(<2 x i64> %a) {
|
|
%tmp.1 = mul nsw <2 x i64> %a, <i64 15, i64 15> ; <<2 x i64>> [#uses=1]
|
|
ret <2 x i64> %tmp.1
|
|
}
|
|
|
|
; CHECK-LABEL: test3_v2i64:
|
|
; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}
|
|
; CHECK-NOT: vmul
|
|
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
|
; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2
|
|
|
|
; negtive constant
|
|
|
|
define <2 x i64> @test4_v2i64(<2 x i64> %a) {
|
|
%tmp.1 = mul nsw <2 x i64> %a, <i64 -16, i64 -16> ; <<2 x i64>> [#uses=1]
|
|
ret <2 x i64> %tmp.1
|
|
}
|
|
|
|
; CHECK-LABEL: test4_v2i64:
|
|
; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}
|
|
; CHECK-NOT: vmul
|
|
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
|
; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]],
|
|
; CHECK-P8-NEXT: vsubudm v{{[0-9]+}}, v[[REG4]], v[[REG3]]
|
|
; CHECK-P9-NEXT: vnegd v[[REG4:[0-9]+]], v[[REG3]]
|
|
|
|
define <2 x i64> @test5_v2i64(<2 x i64> %a) {
|
|
%tmp.1 = mul nsw <2 x i64> %a, <i64 -17, i64 -17> ; <<2 x i64>> [#uses=1]
|
|
ret <2 x i64> %tmp.1
|
|
}
|
|
|
|
; CHECK-LABEL: test5_v2i64:
|
|
; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}
|
|
; CHECK-NOT: vmul
|
|
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
|
; CHECK-NEXT: vaddudm v[[REG4:[0-9]+]], v2, v[[REG3]]
|
|
; CHECK-P8-NEXT: xxlxor v[[REG5:[0-9]+]],
|
|
; CHECK-P8-NEXT: vsubudm v[[REG6:[0-9]+]], v[[REG5]], v[[REG4]]
|
|
; CHECK-P9-NEXT: vnegd v{{[0-9]+}}, v[[REG4]]
|
|
|
|
define <2 x i64> @test6_v2i64(<2 x i64> %a) {
|
|
%tmp.1 = mul nsw <2 x i64> %a, <i64 -15, i64 -15> ; <<2 x i64>> [#uses=1]
|
|
ret <2 x i64> %tmp.1
|
|
}
|
|
|
|
; CHECK-LABEL: test6_v2i64:
|
|
; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}
|
|
; CHECK-NOT: vmul
|
|
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
|
; CHECK-NEXT: vsubudm v{{[0-9]+}}, v2, v[[REG3]]
|
|
|
|
|
|
; boundary case
|
|
|
|
define <2 x i64> @test7_v2i64(<2 x i64> %a) {
|
|
%tmp.1 = mul nsw <2 x i64> %a, <i64 -9223372036854775808, i64 -9223372036854775808> ; <<2 x i64>> [#uses=1]
|
|
ret <2 x i64> %tmp.1
|
|
}
|
|
|
|
; CHECK-LABEL: test7_v2i64:
|
|
; CHECK: xxleqv v[[REG2:[0-9]+]], v[[REG1:[0-9]+]], v[[REG1]]
|
|
; CHECK-NOT: vmul
|
|
; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]]
|
|
|
|
define <2 x i64> @test8_v2i64(<2 x i64> %a) {
|
|
%tmp.1 = mul nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807> ; <<2 x i64>> [#uses=1]
|
|
ret <2 x i64> %tmp.1
|
|
}
|
|
|
|
; CHECK-LABEL: test8_v2i64:
|
|
; CHECK: xxleqv v[[REG2:[0-9]+]], v[[REG1:[0-9]+]], v[[REG1]]
|
|
; CHECK-NOT: vmul
|
|
; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]
|
|
; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2
|