derek.holloway
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111 lines
3.9 KiB
LLVM
111 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s -check-prefixes=CHECK,CHECK-LE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s -check-prefixes=CHECK,CHECK-BE
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; This test case aims to test the builtins for vector rotate instructions
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; on Power10.
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define <1 x i128> @test_vrlq(<1 x i128> %x, <1 x i128> %y) {
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; CHECK-LABEL: test_vrlq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vrlq v2, v3, v2
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; CHECK-NEXT: blr
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%shl.i = shl <1 x i128> %y, %x
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%sub.i = sub <1 x i128> <i128 128>, %x
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%lshr.i = lshr <1 x i128> %y, %sub.i
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%tmp = or <1 x i128> %shl.i, %lshr.i
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ret <1 x i128> %tmp
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}
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define <1 x i128> @test_vrlq_cost_mult8(<1 x i128> %x) {
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; CHECK-LE-LABEL: test_vrlq_cost_mult8:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: plxv v3, .LCPI1_0@PCREL(0), 1
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; CHECK-LE-NEXT: vrlq v2, v3, v2
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_vrlq_cost_mult8:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
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; CHECK-BE-NEXT: lxv v3, 0(r3)
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; CHECK-BE-NEXT: vrlq v2, v3, v2
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; CHECK-BE-NEXT: blr
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%shl.i = shl <1 x i128> <i128 16>, %x
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%sub.i = sub <1 x i128> <i128 128>, %x
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%lshr.i = lshr <1 x i128> <i128 16>, %sub.i
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%tmp = or <1 x i128> %shl.i, %lshr.i
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ret <1 x i128> %tmp
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}
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define <1 x i128> @test_vrlq_cost_non_mult8(<1 x i128> %x) {
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; CHECK-LE-LABEL: test_vrlq_cost_non_mult8:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: plxv v3, .LCPI2_0@PCREL(0), 1
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; CHECK-LE-NEXT: vrlq v2, v3, v2
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_vrlq_cost_non_mult8:
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; CHECK-BE: # %bb.0:
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; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha
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; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l
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; CHECK-BE-NEXT: lxv v3, 0(r3)
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; CHECK-BE-NEXT: vrlq v2, v3, v2
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; CHECK-BE-NEXT: blr
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%shl.i = shl <1 x i128> <i128 4>, %x
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%sub.i = sub <1 x i128> <i128 128>, %x
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%lshr.i = lshr <1 x i128> <i128 4>, %sub.i
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%tmp = or <1 x i128> %shl.i, %lshr.i
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ret <1 x i128> %tmp
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}
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; Function Attrs: nounwind readnone
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define <1 x i128> @test_vrlqmi(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) {
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; CHECK-LABEL: test_vrlqmi:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vrlqmi v3, v2, v4
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; CHECK-NEXT: vmr v2, v3
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128> %a, <1 x i128> %c, <1 x i128> %b)
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ret <1 x i128> %tmp
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}
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; Function Attrs: nounwind readnone
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define <1 x i128> @test_vrlqnm(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) {
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; CHECK-LE-LABEL: test_vrlqnm:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: plxv vs0, .LCPI4_0@PCREL(0), 1
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; CHECK-LE-NEXT: xxperm v3, v4, vs0
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; CHECK-LE-NEXT: vrlqnm v2, v2, v3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_vrlqnm:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
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; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
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; CHECK-BE-NEXT: lxv vs0, 0(r3)
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; CHECK-BE-NEXT: xxperm v4, v3, vs0
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; CHECK-BE-NEXT: vrlqnm v2, v2, v4
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; CHECK-BE-NEXT: blr
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entry:
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%0 = bitcast <1 x i128> %b to <16 x i8>
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%1 = bitcast <1 x i128> %c to <16 x i8>
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%shuffle.i = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%d = bitcast <16 x i8> %shuffle.i to <1 x i128>
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128> %a, <1 x i128> %d)
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ret <1 x i128> %tmp
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}
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; Function Attrs: nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128>, <1 x i128>, <1 x i128>)
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; Function Attrs: nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128>, <1 x i128>)
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