derek.holloway
7502bf64a4
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122 lines
3.4 KiB
LLVM
122 lines
3.4 KiB
LLVM
; Test 64-bit signed comparison in which the second operand is sign-extended
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; from an i16 memory value.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check CGH with no displacement.
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define void @f1(i64 %lhs, ptr %src, ptr %dst) {
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; CHECK-LABEL: f1:
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; CHECK: cgh %r2, 0(%r3)
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; CHECK: br %r14
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%half = load i16, ptr %src
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%rhs = sext i16 %half to i64
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%cond = icmp slt i64 %lhs, %rhs
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%res = select i1 %cond, i64 100, i64 200
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store i64 %res, ptr %dst
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ret void
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}
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; Check the high end of the aligned CGH range.
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define void @f2(i64 %lhs, ptr %src, ptr %dst) {
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; CHECK-LABEL: f2:
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; CHECK: cgh %r2, 524286(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 262143
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i64
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%cond = icmp slt i64 %lhs, %rhs
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%res = select i1 %cond, i64 100, i64 200
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store i64 %res, ptr %dst
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ret void
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}
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; Check the next halfword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f3(i64 %lhs, ptr %src, ptr %dst) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r3, 524288
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; CHECK: cgh %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 262144
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i64
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%cond = icmp slt i64 %lhs, %rhs
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%res = select i1 %cond, i64 100, i64 200
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store i64 %res, ptr %dst
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ret void
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}
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; Check the high end of the negative aligned CGH range.
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define void @f4(i64 %lhs, ptr %src, ptr %dst) {
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; CHECK-LABEL: f4:
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; CHECK: cgh %r2, -2(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -1
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i64
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%cond = icmp slt i64 %lhs, %rhs
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%res = select i1 %cond, i64 100, i64 200
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store i64 %res, ptr %dst
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ret void
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}
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; Check the low end of the CGH range.
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define void @f5(i64 %lhs, ptr %src, ptr %dst) {
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; CHECK-LABEL: f5:
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; CHECK: cgh %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -262144
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i64
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%cond = icmp slt i64 %lhs, %rhs
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%res = select i1 %cond, i64 100, i64 200
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store i64 %res, ptr %dst
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ret void
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}
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; Check the next halfword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f6(i64 %lhs, ptr %src, ptr %dst) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r3, -524290
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; CHECK: cgh %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i16, ptr %src, i64 -262145
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i64
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%cond = icmp slt i64 %lhs, %rhs
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%res = select i1 %cond, i64 100, i64 200
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store i64 %res, ptr %dst
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ret void
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}
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; Check that CGH allows an index.
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define void @f7(i64 %lhs, i64 %base, i64 %index, ptr %dst) {
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; CHECK-LABEL: f7:
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; CHECK: cgh %r2, 4096({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to ptr
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%half = load i16, ptr %ptr
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%rhs = sext i16 %half to i64
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%cond = icmp slt i64 %lhs, %rhs
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%res = select i1 %cond, i64 100, i64 200
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store i64 %res, ptr %dst
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ret void
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}
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; Check the comparison can be reversed if that allows CGH to be used.
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define double @f8(double %a, double %b, i64 %rhs, ptr %src) {
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; CHECK-LABEL: f8:
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; CHECK: cgh %r2, 0(%r3)
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; CHECK-NEXT: bhr %r14
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; CHECK: ldr %f0, %f2
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; CHECK: br %r14
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%half = load i16, ptr %src
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%lhs = sext i16 %half to i64
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%cond = icmp slt i64 %lhs, %rhs
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%res = select i1 %cond, double %a, double %b
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ret double %res
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}
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