derek.holloway
7502bf64a4
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350 lines
11 KiB
LLVM
350 lines
11 KiB
LLVM
; Test f32 and v4f32 comparisons on z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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; Test oeq.
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define <4 x i32> @f1(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vfcesb %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%cmp = fcmp oeq <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test one.
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define <4 x i32> @f2(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f2:
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; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26
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; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v26, %v28
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; CHECK: vo %v24, [[REG1]], [[REG2]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp one <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ogt.
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define <4 x i32> @f3(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vfchsb %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%cmp = fcmp ogt <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test oge.
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define <4 x i32> @f4(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vfchesb %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%cmp = fcmp oge <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ole.
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define <4 x i32> @f5(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f5:
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; CHECK: vfchesb %v24, %v28, %v26
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; CHECK-NEXT: br %r14
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%cmp = fcmp ole <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test olt.
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define <4 x i32> @f6(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f6:
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; CHECK: vfchsb %v24, %v28, %v26
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; CHECK-NEXT: br %r14
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%cmp = fcmp olt <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ueq.
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define <4 x i32> @f7(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f7:
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; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26
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; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v26, %v28
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; CHECK: vno %v24, [[REG1]], [[REG2]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ueq <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test une.
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define <4 x i32> @f8(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f8:
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; CHECK: vfcesb [[REG:%v[0-9]+]], %v26, %v28
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp une <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ugt.
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define <4 x i32> @f9(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f9:
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; CHECK: vfchesb [[REG:%v[0-9]+]], %v28, %v26
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ugt <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test uge.
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define <4 x i32> @f10(<4 x i32> %dummy, <4 x float> %val1,
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<4 x float> %val2) {
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; CHECK-LABEL: f10:
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; CHECK: vfchsb [[REG:%v[0-9]+]], %v28, %v26
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp uge <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ule.
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define <4 x i32> @f11(<4 x i32> %dummy, <4 x float> %val1,
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<4 x float> %val2) {
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; CHECK-LABEL: f11:
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; CHECK: vfchsb [[REG:%v[0-9]+]], %v26, %v28
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ule <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ult.
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define <4 x i32> @f12(<4 x i32> %dummy, <4 x float> %val1,
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<4 x float> %val2) {
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; CHECK-LABEL: f12:
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; CHECK: vfchesb [[REG:%v[0-9]+]], %v26, %v28
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ult <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test ord.
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define <4 x i32> @f13(<4 x i32> %dummy, <4 x float> %val1,
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<4 x float> %val2) {
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; CHECK-LABEL: f13:
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; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26
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; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v26, %v28
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; CHECK: vo %v24, [[REG1]], [[REG2]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ord <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test uno.
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define <4 x i32> @f14(<4 x i32> %dummy, <4 x float> %val1,
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<4 x float> %val2) {
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; CHECK-LABEL: f14:
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; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26
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; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v26, %v28
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; CHECK: vno %v24, [[REG1]], [[REG2]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp uno <4 x float> %val1, %val2
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%ret = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %ret
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}
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; Test oeq selects.
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define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f15:
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; CHECK: vfcesb [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp oeq <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test one selects.
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define <4 x float> @f16(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f16:
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; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24
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; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v24, %v26
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; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp one <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test ogt selects.
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define <4 x float> @f17(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f17:
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; CHECK: vfchsb [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ogt <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test oge selects.
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define <4 x float> @f18(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f18:
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; CHECK: vfchesb [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp oge <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test ole selects.
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define <4 x float> @f19(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f19:
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; CHECK: vfchesb [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ole <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test olt selects.
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define <4 x float> @f20(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f20:
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; CHECK: vfchsb [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp olt <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test ueq selects.
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define <4 x float> @f21(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f21:
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; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24
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; CHECK-DAG: vfchsb [[REG2:%v[0-9]+]], %v24, %v26
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; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ueq <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test une selects.
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define <4 x float> @f22(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f22:
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; CHECK: vfcesb [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp une <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test ugt selects.
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define <4 x float> @f23(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f23:
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; CHECK: vfchesb [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ugt <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test uge selects.
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define <4 x float> @f24(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f24:
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; CHECK: vfchsb [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp uge <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test ule selects.
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define <4 x float> @f25(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f25:
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; CHECK: vfchsb [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ule <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test ult selects.
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define <4 x float> @f26(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f26:
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; CHECK: vfchesb [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ult <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test ord selects.
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define <4 x float> @f27(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f27:
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; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24
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; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v24, %v26
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; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = fcmp ord <4 x float> %val1, %val2
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%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
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ret <4 x float> %ret
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}
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; Test uno selects.
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define <4 x float> @f28(<4 x float> %val1, <4 x float> %val2,
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<4 x float> %val3, <4 x float> %val4) {
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; CHECK-LABEL: f28:
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; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v26, %v24
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; CHECK-DAG: vfchesb [[REG2:%v[0-9]+]], %v24, %v26
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; CHECK: vo [[REG:%v[0-9]+]], [[REG1]], [[REG2]]
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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|
%cmp = fcmp uno <4 x float> %val1, %val2
|
|
%ret = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
|
|
ret <4 x float> %ret
|
|
}
|
|
|
|
; Test an f32 comparison that uses vector registers.
|
|
define i64 @f29(i64 %a, i64 %b, float %f1, <4 x float> %vec) {
|
|
; CHECK-LABEL: f29:
|
|
; CHECK: wfcsb %f0, %v24
|
|
; CHECK-NEXT: locgrne %r2, %r3
|
|
; CHECK: br %r14
|
|
%f2 = extractelement <4 x float> %vec, i32 0
|
|
%cond = fcmp oeq float %f1, %f2
|
|
%res = select i1 %cond, i64 %a, i64 %b
|
|
ret i64 %res
|
|
}
|