derek.holloway
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67 lines
2.2 KiB
LLVM
67 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown -mattr=+sse2,+pclmul | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown -mattr=+avx2,+pclmul | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown -mattr=+avx512vl,+vpclmulqdq | FileCheck %s --check-prefix=AVX
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declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8) nounwind readnone
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define <2 x i64> @commute_lq_lq(ptr %a0, <2 x i64> %a1) #0 {
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; SSE-LABEL: commute_lq_lq:
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; SSE: # %bb.0:
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; SSE-NEXT: pclmulqdq $0, (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_lq_lq:
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; AVX: # %bb.0:
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; AVX-NEXT: vpclmulqdq $0, (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = load <2 x i64>, ptr %a0
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%2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 0)
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ret <2 x i64> %2
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}
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define <2 x i64> @commute_lq_hq(ptr %a0, <2 x i64> %a1) #0 {
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; SSE-LABEL: commute_lq_hq:
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; SSE: # %bb.0:
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; SSE-NEXT: pclmulqdq $1, (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_lq_hq:
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; AVX: # %bb.0:
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; AVX-NEXT: vpclmulqdq $1, (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = load <2 x i64>, ptr %a0
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%2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 16)
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ret <2 x i64> %2
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}
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define <2 x i64> @commute_hq_lq(ptr %a0, <2 x i64> %a1) #0 {
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; SSE-LABEL: commute_hq_lq:
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; SSE: # %bb.0:
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; SSE-NEXT: pclmulqdq $16, (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_hq_lq:
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; AVX: # %bb.0:
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; AVX-NEXT: vpclmulqdq $16, (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = load <2 x i64>, ptr %a0
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%2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 1)
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ret <2 x i64> %2
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}
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define <2 x i64> @commute_hq_hq(ptr %a0, <2 x i64> %a1) #0 {
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; SSE-LABEL: commute_hq_hq:
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; SSE: # %bb.0:
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; SSE-NEXT: pclmulqdq $17, (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: commute_hq_hq:
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; AVX: # %bb.0:
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; AVX-NEXT: vpclmulqdq $17, (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = load <2 x i64>, ptr %a0
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%2 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %a1, i8 17)
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ret <2 x i64> %2
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}
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