TheRock/compiler/amd-llvm/llvm/test/Transforms/LoopVectorize/nested-outer-loop-vect.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -passes=loop-vectorize -enable-vplan-native-path -verify-loop-info -verify-dom-info -S %s | FileCheck %s

@arr2 = external global [8 x i32], align 16
@arr = external global [8 x [8 x i32]], align 16

define void @nested_outer_loop_vect(i32 %n, i64 %outer_tc) {
; CHECK-LABEL: define void @nested_outer_loop_vect(
; CHECK-SAME: i32 [[N:%.*]], i64 [[OUTER_TC:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[LOOP0_HEADER:.*]]
; CHECK:       [[LOOP0_HEADER]]:
; CHECK-NEXT:    [[OUTER_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[OUTER_IV_NEXT:%.*]], %[[LOOP0_LATCH:.*]] ]
; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[N]], i64 0
; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_LATCH:.*]] ]
; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_LATCH]] ]
; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [8 x i32], ptr @arr2, i64 0, <4 x i64> [[VEC_IND]]
; CHECK-NEXT:    [[TMP1:%.*]] = trunc <4 x i64> [[VEC_IND]] to <4 x i32>
; CHECK-NEXT:    call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[TMP1]], <4 x ptr> align 4 [[TMP0]], <4 x i1> splat (i1 true))
; CHECK-NEXT:    [[TMP2:%.*]] = add nsw <4 x i32> [[TMP1]], [[BROADCAST_SPLAT]]
; CHECK-NEXT:    br label %[[LOOP2_HEADER1:.*]]
; CHECK:       [[LOOP2_HEADER1]]:
; CHECK-NEXT:    [[TMP3:%.*]] = phi <4 x i64> [ zeroinitializer, %[[VECTOR_BODY]] ], [ [[TMP5:%.*]], %[[LOOP2_HEADER1]] ]
; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [8 x [8 x i32]], ptr @arr, i64 0, <4 x i64> [[TMP3]], <4 x i64> [[VEC_IND]]
; CHECK-NEXT:    call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> [[TMP2]], <4 x ptr> align 4 [[TMP4]], <4 x i1> splat (i1 true))
; CHECK-NEXT:    [[TMP5]] = add nuw nsw <4 x i64> [[TMP3]], splat (i64 1)
; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq <4 x i64> [[TMP5]], splat (i64 8)
; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <4 x i1> [[TMP6]], i64 0
; CHECK-NEXT:    br i1 [[TMP7]], label %[[VECTOR_LATCH]], label %[[LOOP2_HEADER1]]
; CHECK:       [[VECTOR_LATCH]]:
; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT:    [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
; CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 8
; CHECK-NEXT:    br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK:       [[MIDDLE_BLOCK]]:
; CHECK-NEXT:    br label %[[LOOP0_LATCH]]
; CHECK:       [[LOOP0_LATCH]]:
; CHECK-NEXT:    [[OUTER_IV_NEXT]] = add nuw nsw i64 [[OUTER_IV]], 1
; CHECK-NEXT:    [[OUTER_COND:%.*]] = icmp eq i64 [[OUTER_IV_NEXT]], [[OUTER_TC]]
; CHECK-NEXT:    br i1 [[OUTER_COND]], label %[[EXIT:.*]], label %[[LOOP0_HEADER]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop0.header

loop0.header:
  %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %loop0.latch ]
  br label %loop1.header

loop1.header:
  %loop1.iv = phi i64 [ 0, %loop0.header ], [ %loop1.iv.next, %loop1.latch ]
  %gep.arr2 = getelementptr inbounds [8 x i32], ptr @arr2, i64 0, i64 %loop1.iv
  %0 = trunc i64 %loop1.iv to i32
  store i32 %0, ptr %gep.arr2, align 4
  %1 = trunc i64 %loop1.iv to i32
  %add = add nsw i32 %1, %n
  br label %loop2.header

loop2.header:
  %loop2.iv = phi i64 [ 0, %loop1.header ], [ %loop2.iv.next, %loop2.header ]
  %gep.arr = getelementptr inbounds [8 x [8 x i32]], ptr @arr, i64 0, i64 %loop2.iv, i64 %loop1.iv
  store i32 %add, ptr %gep.arr, align 4
  %loop2.iv.next = add nuw nsw i64 %loop2.iv, 1
  %exitcond.loop2 = icmp eq i64 %loop2.iv.next, 8
  br i1 %exitcond.loop2, label %loop1.latch, label %loop2.header

loop1.latch:
  %loop1.iv.next = add nuw nsw i64 %loop1.iv, 1
  %exitcond.loop1 = icmp eq i64 %loop1.iv.next, 8
  br i1 %exitcond.loop1, label %loop0.latch, label %loop1.header, !llvm.loop !1

loop0.latch:
  %outer.iv.next = add nuw nsw i64 %outer.iv, 1
  %outer.cond = icmp eq i64 %outer.iv.next, %outer_tc
  br i1 %outer.cond, label %exit, label %loop0.header

exit:
  ret void
}

!1 = distinct !{!1, !2, !3}
!2 = !{!"llvm.loop.vectorize.width", i32 4}
!3 = !{!"llvm.loop.vectorize.enable", i1 true}