derek.holloway
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21 lines
1.1 KiB
LLVM
21 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s
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; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s
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; This test checks that SROA runs mem2reg on arrays of scalable vectors.
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define [ 2 x <vscale x 4 x i32> ] @alloca(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
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; CHECK-LABEL: define [2 x <vscale x 4 x i32>] @alloca
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; CHECK-SAME: (<vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32> [[Y:%.*]]) {
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; CHECK-NEXT: [[AGG0:%.*]] = insertvalue [2 x <vscale x 4 x i32>] poison, <vscale x 4 x i32> [[X]], 0
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; CHECK-NEXT: [[AGG1:%.*]] = insertvalue [2 x <vscale x 4 x i32>] [[AGG0]], <vscale x 4 x i32> [[Y]], 1
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; CHECK-NEXT: ret [2 x <vscale x 4 x i32>] [[AGG1]]
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;
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%addr = alloca [ 2 x <vscale x 4 x i32> ], align 4
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%agg0 = insertvalue [ 2 x <vscale x 4 x i32> ] poison, <vscale x 4 x i32> %x, 0
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%agg1 = insertvalue [ 2 x <vscale x 4 x i32> ] %agg0, <vscale x 4 x i32> %y, 1
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store [ 2 x <vscale x 4 x i32> ] %agg1, ptr %addr, align 4
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%val = load [ 2 x <vscale x 4 x i32> ], ptr %addr, align 4
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ret [ 2 x <vscale x 4 x i32> ] %val
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}
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