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292 lines
10 KiB
LLVM
292 lines
10 KiB
LLVM
; RUN: llvm-as < %s | llvm-spirv -spirv-text -spirv-allow-unknown-intrinsics -o %t
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; RUN: FileCheck < %t %s
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; CHECK: Name [[#FEATURE_PREDICATE_IDS:]] "llvm.amdgcn.feature.predicate.ids"
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; CHECK: Name [[#ASHR_PK_I8_I32:]] "llvm.amdgcn.ashr.pk.i8.i32"
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; CHECK: Name [[#SET_FPENV_I64:]] "llvm.set.fpenv.i64"
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; CHECK: Name [[#S_SLEEP_VAR:]] "llvm.amdgcn.s.sleep.var"
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; CHECK: Name [[#S_WAIT_EVENT_EXPORT_READY:]] "llvm.amdgcn.s.wait.event.export.ready"
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; CHECK: Name [[#S_TTRACEDATA_IMM:]] "llvm.amdgcn.s.ttracedata.imm"
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; CHECK: Name [[#KERNEL:]] "kernel"
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; CHECK: Decorate [[#IS_GFX950:]] SpecId 8
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; CHECK: Decorate [[#IS_GFX1201:]] SpecId 3
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; CHECK: Decorate [[#HAS_GFX12_INSTS:]] SpecId 7
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; CHECK: Decorate [[#IS_GFX906:]] SpecId 6
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; CHECK: Decorate [[#IS_GFX1010:]] SpecId 4
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; CHECK: Decorate [[#IS_GFX1101:]] SpecId 5
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; CHECK: Decorate [[#IS_GFX1101_1:]] SpecId 5
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; CHECK: Decorate [[#IS_GFX1010_1:]] SpecId 4
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; CHECK: Decorate [[#IS_GFX1201_1:]] SpecId 3
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; CHECK: Decorate [[#HAS_GFX11_INSTS:]] SpecId 0
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; CHECK: Decorate [[#HAS_GFX10_INSTS:]] SpecId 2
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; CHECK: Decorate [[#HAS_GFX1250_INSTS:]] SpecId 1
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; CHECK: Decorate [[#HAS_GFX11_INSTS_1:]] SpecId 0
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; CHECK: TypeInt [[#UCHAR:]] 8
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; CHECK: Constant [[#]] [[#FEATURE_PREDICATE_IDS_MAP_STRLEN:]] 137
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; CHECK: TypeArray [[#FEATURE_PREDICATE_IDS_MAP_STRTY:]] [[#UCHAR]] [[#FEATURE_PREDICATE_IDS_MAP_STRLEN]]
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; CHECK: TypeBool [[#BOOL:]]
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; CHECK: ConstantComposite [[#FEATURE_PREDICATE_IDS_MAP_STRTY]] [[#FEATURE_PREDICATE_IDS_MAP_STRVAL:]]
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; CHECK: Variable [[#]] [[#FEATURE_PREDICATE_IDS]] [[#]] [[#FEATURE_PREDICATE_IDS_MAP_STRVAL]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#IS_GFX950]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#IS_GFX1201]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#HAS_GFX12_INSTS]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#IS_GFX906]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#IS_GFX1010]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#IS_GFX1101]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#IS_GFX1101_1]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#IS_GFX1010_1]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#IS_GFX1201_1]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#HAS_GFX11_INSTS]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#HAS_GFX10_INSTS]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#HAS_GFX1250_INSTS]]
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; CHECK: SpecConstantFalse [[#BOOL]] [[#HAS_GFX11_INSTS_1]]
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
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target triple = "spirv64-amd-amdhsa"
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declare void @llvm.amdgcn.s.monitor.sleep(i16 %immarg) addrspace(4)
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declare void @llvm.amdgcn.s.sleep(i32 %immarg) addrspace(4)
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declare i1 @llvm.spv.named.boolean.spec.constant(i32, i1, metadata) addrspace(4)
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declare i16 @llvm.amdgcn.ashr.pk.i8.i32(i32, i32, i32) addrspace(4) #3
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declare void @llvm.set.fpenv.i64(i64) addrspace(4) #4
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declare void @llvm.amdgcn.s.sleep.var(i32) addrspace(4) #5
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declare void @llvm.amdgcn.s.wait.event.export.ready() addrspace(4) #5
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declare void @llvm.amdgcn.s.ttracedata.imm(i16 %immarg) addrspace(4) #6
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@p = external addrspace(1) global i32
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@g = external addrspace(1) constant i32
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define void @kernel() addrspace(4) {
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; CHECK-DAG: Function [[#]] [[#KERNEL]]
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; CHECK: Label 55
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; CHECK: Load 2 94 5 2 4
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; CHECK: BranchConditional [[#IS_GFX950]] 56 57
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; CHECK: Label 56
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; CHECK: FunctionCall 36 98 [[#ASHR_PK_I8_I32]] 97 97 97
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; CHECK: Branch 58
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; CHECK: Label 57
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; CHECK: FunctionCall 42 100 [[#SET_FPENV_I64]] 99
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; CHECK: Branch 58
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; CHECK: Label 58
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; CHECK: BranchConditional [[#IS_GFX1201]] 60 59
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; CHECK: Label 59
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; CHECK: BranchConditional [[#HAS_GFX12_INSTS]] 60 61
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; CHECK: Label 60
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; CHECK: FunctionCall 42 103 [[#S_SLEEP_VAR]] 94
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; CHECK: Branch 61
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; CHECK: Label 61
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; CHECK: BranchConditional [[#IS_GFX906]] 63 62
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; CHECK: Label 62
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; CHECK: FunctionCall 42 105 [[#S_WAIT_EVENT_EXPORT_READY]]
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; CHECK: Branch 67
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; CHECK: Label 63
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; CHECK: BranchConditional [[#IS_GFX1010]] 65 64
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; CHECK: Label 64
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; CHECK: BranchConditional [[#IS_GFX1101]] 65 66
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; CHECK: Label 65
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; CHECK: FunctionCall 42 109 [[#S_TTRACEDATA_IMM]] 108
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; CHECK: Branch 66
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; CHECK: Label 66
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; CHECK: Branch 67
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; CHECK: Label 67
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; CHECK: Branch 68
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; CHECK: Label 68
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; CHECK: BranchConditional [[#IS_GFX1101_1]] 69 70
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; CHECK: Label 69
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; CHECK: Load 2 111 4 2 4
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; CHECK: IAdd 2 113 112 94
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; CHECK: Store 4 113 2 4
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; CHECK: Branch 70
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; CHECK: Label 70
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; CHECK: Branch 71
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; CHECK: Label 71
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; CHECK: Load 2 114 4 2 4
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; CHECK: ISub 2 116 115 94
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; CHECK: Store 4 116 2 4
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; CHECK: Branch 72
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; CHECK: Label 72
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; CHECK: BranchConditional [[#IS_GFX1010_1]] 73 74
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; CHECK: Label 73
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; CHECK: Branch 74
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; CHECK: Label 74
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; CHECK: Phi 95 119 118 72 118 73
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; CHECK: BranchConditional 119 71 75
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; CHECK: Label 75
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; CHECK: Branch 76
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; CHECK: Label 76
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; CHECK: BranchConditional [[#IS_GFX1201_1]] 77 79
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; CHECK: Label 77
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; CHECK: Branch 79
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; CHECK: Label 78
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; CHECK: Load 2 121 4 2 4
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; CHECK: IAdd 2 123 121 122
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; CHECK: Store 4 123 2 4
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; CHECK: Branch 76
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; CHECK: Label 79
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; CHECK: BranchConditional [[#HAS_GFX11_INSTS]] 80 81
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; CHECK: Label 80
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; CHECK: FunctionCall 42 125 [[#S_WAIT_EVENT_EXPORT_READY]]
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; CHECK: Branch 84
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; CHECK: Label 81
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; CHECK: BranchConditional [[#HAS_GFX10_INSTS]] 82 83
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; CHECK: Label 82
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; CHECK: FunctionCall 42 127 [[#S_TTRACEDATA_IMM]] 108
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; CHECK: Branch 83
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; CHECK: Label 83
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; CHECK: Branch 84
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; CHECK: Label 84
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; CHECK: Branch 85
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; CHECK: Label 85
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; CHECK: Load 2 128 4 2 4
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; CHECK: ISub 2 130 129 94
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; CHECK: Store 4 130 2 4
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; CHECK: Branch 86
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; CHECK: Label 86
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; CHECK: BranchConditional [[#HAS_GFX1250_INSTS]] 87 88
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; CHECK: Label 87
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; CHECK: Branch 88
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; CHECK: Label 88
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; CHECK: Phi 95 132 118 86 118 87
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; CHECK: BranchConditional 132 85 89
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; CHECK: Label 89
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; CHECK: Branch 90
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; CHECK: Label 90
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; CHECK: BranchConditional [[#HAS_GFX11_INSTS_1]] 91 93
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entry:
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%x = load i32, ptr addrspace(1) @g
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%is.gfx950. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !9)
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br i1 %is.gfx950., label %cond.true, label %cond.false
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cond.true:
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%0 = call addrspace(4) i16 @llvm.amdgcn.ashr.pk.i8.i32(i32 8, i32 8, i32 8)
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br label %cond.end
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cond.false:
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call addrspace(4) void @llvm.set.fpenv.i64(i64 -1)
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br label %cond.end
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cond.end:
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%is.gfx1201. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !10)
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br i1 %is.gfx1201., label %if.then, label %lor.lhs.false
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lor.lhs.false:
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%has.gfx12-insts. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !11)
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br i1 %has.gfx12-insts., label %if.then, label %if.end
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if.then:
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call addrspace(4) void @llvm.amdgcn.s.sleep.var(i32 %x)
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br label %if.end
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if.end:
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%is.gfx906. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !12)
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br i1 %is.gfx906., label %if.else, label %if.then2
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if.then2:
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call addrspace(4) void @llvm.amdgcn.s.wait.event.export.ready()
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br label %if.end6
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if.else:
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%is.gfx1010. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !13)
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br i1 %is.gfx1010., label %if.then4, label %lor.lhs.false3
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lor.lhs.false3:
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%is.gfx1101. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !14)
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br i1 %is.gfx1101., label %if.then4, label %if.end5
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if.then4:
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call addrspace(4) void @llvm.amdgcn.s.ttracedata.imm(i16 1)
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br label %if.end5
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if.end5:
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br label %if.end6
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if.end6:
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br label %while.cond
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while.cond:
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%is.gfx1101.7 = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !14)
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br i1 %is.gfx1101.7, label %while.body, label %while.end
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while.body:
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%4 = load i32, ptr addrspace(1) @p
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%add = add i32 4, %x
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store i32 %add, ptr addrspace(1) @p
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br label %while.end
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while.end:
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br label %do.body
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do.body:
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%7 = load i32, ptr addrspace(1) @p
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%sub = sub i32 7, %x
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store i32 %sub, ptr addrspace(1) @p
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br label %do.cond
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do.cond:
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%is.gfx1010.8 = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !13)
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br i1 %is.gfx1010.8, label %land.rhs, label %land.end
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land.rhs:
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br label %land.end
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land.end:
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%c = phi i1 [ false, %do.cond ], [ false, %land.rhs ]
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br i1 %c, label %do.body, label %do.end
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do.end:
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br label %for.cond
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for.cond:
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%is.gfx1201.9 = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !10)
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br i1 %is.gfx1201.9, label %for.body, label %for.end
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for.body:
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br label %for.end
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for.inc:
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%9 = load i32, ptr addrspace(1) @p
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%inc = add i32 %9, 1
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store i32 %inc, ptr addrspace(1) @p
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br label %for.cond
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for.end:
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%has.gfx11-insts. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !18)
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br i1 %has.gfx11-insts., label %if.then10, label %if.else11
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if.then10:
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call addrspace(4) void @llvm.amdgcn.s.wait.event.export.ready()
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br label %if.end14
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if.else11:
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%has.gfx10-insts. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !19)
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br i1 %has.gfx10-insts., label %if.then12, label %if.end13
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if.then12:
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call addrspace(4) void @llvm.amdgcn.s.ttracedata.imm(i16 1)
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br label %if.end13
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if.end13:
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br label %if.end14
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if.end14:
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br label %do.body15
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do.body15:
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%12 = load i32, ptr addrspace(1) @p
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%sub16 = sub i32 12, %x
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store i32 %sub16, ptr addrspace(1) @p
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br label %do.cond17
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do.cond17:
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%has.gfx1250-insts. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !20)
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br i1 %has.gfx1250-insts., label %land.rhs9, label %land.end10
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land.rhs9:
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br label %land.end10
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land.end10:
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%c1 = phi i1 [ false, %do.cond17 ], [ false, %land.rhs9 ]
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br i1 %c1, label %do.body15, label %do.end18
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do.end18:
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br label %for.cond19
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for.cond19:
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%has.gfx11-insts.20 = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !18)
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br i1 %has.gfx11-insts.20, label %for.body21, label %for.end24
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for.body21:
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br label %for.end24
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for.inc22:
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%14 = load i32, ptr addrspace(1) @p
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%inc23 = add i32 14, 1
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store i32 %inc23, ptr addrspace(1) @p
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br label %for.cond19
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for.end24:
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ret void
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}
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!spirv.Generator = !{!4}
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!4 = !{i16 6, i16 65535}
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!9 = !{!"is.gfx950"}
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!10 = !{!"is.gfx1201"}
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!11 = !{!"has.gfx12-insts"}
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!12 = !{!"is.gfx906"}
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!13 = !{!"is.gfx1010"}
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!14 = !{!"is.gfx1101"}
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!18 = !{!"has.gfx11-insts"}
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!19 = !{!"has.gfx10-insts"}
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!20 = !{!"has.gfx1250-insts"}
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