derek.holloway
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103 lines
1.8 KiB
ArmAsm
103 lines
1.8 KiB
ArmAsm
# mach: aarch64
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# Check the load single 1-element structure to one lane instructions:
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# ld1, ld2, ld3, ld4.
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# Check the addressing modes: no offset, post-index immediate offset,
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# post-index register offset.
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.include "testutils.inc"
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.data
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.align 4
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input:
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.word 0x04030201
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.word 0x08070605
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.word 0x0c0b0a09
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.word 0x100f0e0d
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.word 0x14131211
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.word 0x18171615
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.word 0x1c1b1a19
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.word 0x201f1e1d
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start
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adrp x0, input
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add x0, x0, :lo12:input
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mov x2, x0
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mov x3, #1
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mov x4, #4
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ld1 {v0.b}[0], [x2], 1
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ld1 {v0.b}[1], [x2], x3
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ld1 {v0.h}[1], [x2], 2
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ld1 {v0.s}[1], [x2], x4
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ld1 {v0.d}[1], [x2]
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addv b1, v0.16b
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mov x5, v1.d[0]
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cmp x5, #136
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bne .Lfailure
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mov x2, x0
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mov x3, #16
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mov x4, #4
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ld2 {v0.d, v1.d}[0], [x2], x3
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ld2 {v0.s, v1.s}[2], [x2], 8
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ld2 {v0.h, v1.h}[6], [x2], x4
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ld2 {v0.b, v1.b}[14], [x2], 2
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ld2 {v0.b, v1.b}[15], [x2]
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addv b2, v0.16b
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addv b3, v1.16b
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mov x5, v2.d[0]
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mov x6, v3.d[0]
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cmp x5, #221
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bne .Lfailure
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cmp x6, #51
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bne .Lfailure
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mov x2, x0
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ld3 {v0.s, v1.s, v2.s}[0], [x2], 12
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ld3 {v0.s, v1.s, v2.s}[1], [x2]
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mov x2, x0
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mov x3, #12
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ld3 {v0.s, v1.s, v2.s}[2], [x2], x3
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ld3 {v0.s, v1.s, v2.s}[3], [x2]
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addv b3, v0.16b
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addv b4, v1.16b
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addv b5, v2.16b
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mov x4, v3.d[0]
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mov x5, v4.d[0]
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mov x6, v5.d[0]
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cmp x4, #136
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bne .Lfailure
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cmp x5, #200
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bne .Lfailure
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cmp x6, #8
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bne .Lfailure
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mov x2, x0
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ld4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16
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ld4 {v0.s, v1.s, v2.s, v3.s}[1], [x2]
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mov x2, x0
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mov x3, #16
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ld4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], x3
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ld4 {v0.s, v1.s, v2.s, v3.s}[3], [x2]
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addv b4, v0.16b
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addv b5, v1.16b
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addv b6, v2.16b
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addv b7, v3.16b
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mov x4, v4.d[0]
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mov x5, v5.d[0]
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mov x6, v6.d[0]
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mov x7, v7.d[0]
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cmp x4, #168
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bne .Lfailure
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cmp x5, #232
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bne .Lfailure
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cmp x6, #40
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bne .Lfailure
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cmp x7, #104
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bne .Lfailure
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pass
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.Lfailure:
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fail
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