derek.holloway
7502bf64a4
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62 lines
1.2 KiB
ArmAsm
62 lines
1.2 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/seq/se_ssync/se_ssync.dsp
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// Description: Test SSYNC by writing a bunch of MMRs and verifying read
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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//
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// Constants and Defines
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//
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include(selfcheck.inc)
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include(std.inc)
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include(mmrs.inc)
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include(symtable.inc)
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#ifndef STACKSIZE
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#define STACKSIZE 0x10 // change for how much stack you need
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#endif
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LD32(p0, EVT5);
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LD32(r0, 0x55555555);
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LD32(p1, EVT6);
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LD32(r1, 0xAAAAAAAA);
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LD32(p2, EVT7);
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LD32(r2, 0xBABEFACE);
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LD32(p3, EVT8);
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LD32(r3, 0xCFCFCFCF);
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LD32(p4, EVT9);
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LD32(r4, 0xDEADBEEF);
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LD32(p5, EVT10);
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LD32(r5, 0xBAD1BAD1);
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[ P0 ] = R0; // write the MMRS
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[ P1 ] = R1;
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[ P2 ] = R2;
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[ P3 ] = R3;
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[ P4 ] = R4;
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[ P5 ] = R5;
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SSYNC; // wait for it
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R7 = [ P5 ]; // read back MMRs
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R6 = [ P4 ]; // should be updated
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R5 = [ P3 ];
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R4 = [ P2 ];
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R3 = [ P1 ];
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R2 = [ P0 ];
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CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
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CHECKREG(r2, 0x55555555);
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CHECKREG(r3, 0xAAAAAAAA);
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CHECKREG(r4, 0xBABEFACE);
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CHECKREG(r5, 0xCFCFCFCF);
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CHECKREG(r6, 0xDEADBEEF);
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CHECKREG(r7, 0xBAD1BAD1);
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dbg_pass;
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