derek.holloway
7502bf64a4
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301 lines
12 KiB
YAML
301 lines
12 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefixes=CHECK,RV64I
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# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB_OR_RV64ZBKB
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# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefixes=CHECK,RV64ZBB_OR_RV64ZBKB
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---
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name: rotl_i8
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body: |
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bb.1:
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liveins: $x10, $x11
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; CHECK-LABEL: name: rotl_i8
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; CHECK: liveins: $x10, $x11
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64)
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; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
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; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
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; CHECK-NEXT: $x10 = COPY [[OR]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%2:_(s64) = COPY $x10
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%0:_(s8) = G_TRUNC %2(s64)
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%3:_(s64) = COPY $x11
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%1:_(s8) = G_TRUNC %3(s64)
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%4:_(s8) = G_ROTL %0, %1(s8)
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%5:_(s64) = G_ANYEXT %4(s8)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: rotl_i16
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body: |
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bb.1:
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liveins: $x10, $x11
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; CHECK-LABEL: name: rotl_i16
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; CHECK: liveins: $x10, $x11
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64)
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; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
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; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
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; CHECK-NEXT: $x10 = COPY [[OR]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%2:_(s64) = COPY $x10
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%0:_(s16) = G_TRUNC %2(s64)
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%3:_(s64) = COPY $x11
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%1:_(s16) = G_TRUNC %3(s64)
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%4:_(s16) = G_ROTL %0, %1(s16)
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%5:_(s64) = G_ANYEXT %4(s16)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: rotl_i32
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body: |
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bb.1:
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liveins: $x10, $x11
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; RV64I-LABEL: name: rotl_i32
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
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; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
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; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32
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; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
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; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND]]
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; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]]
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; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND1]]
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; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SLLW]], [[SRLW]]
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; RV64I-NEXT: $x10 = COPY [[OR]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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;
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; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotl_i32
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; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
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; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
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; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROLW:%[0-9]+]]:_(s64) = G_ROLW [[COPY]], [[COPY1]]
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; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROLW]](s64)
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; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
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%2:_(s64) = COPY $x10
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%0:_(s32) = G_TRUNC %2(s64)
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%3:_(s64) = COPY $x11
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%1:_(s32) = G_TRUNC %3(s64)
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%4:_(s32) = G_ROTL %0, %1(s32)
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%5:_(s64) = G_ANYEXT %4(s32)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: rotl_i64
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body: |
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bb.1:
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liveins: $x10, $x11
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; RV64I-LABEL: name: rotl_i64
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
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; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
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; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
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; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64)
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; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
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; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND1]](s64)
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; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SHL]], [[LSHR]]
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; RV64I-NEXT: $x10 = COPY [[OR]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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;
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; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotl_i64
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; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
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; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
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; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s64) = G_ROTL [[COPY]], [[COPY1]](s64)
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; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROTL]](s64)
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; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
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%0:_(s64) = COPY $x10
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%1:_(s64) = COPY $x11
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%2:_(s64) = G_ROTL %0, %1(s64)
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: rotr_i8
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body: |
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bb.1:
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liveins: $x10, $x11
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; CHECK-LABEL: name: rotr_i8
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; CHECK: liveins: $x10, $x11
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]]
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; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64)
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; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND3]](s64)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[LSHR]], [[SHL]]
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; CHECK-NEXT: $x10 = COPY [[OR]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%2:_(s64) = COPY $x10
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%0:_(s8) = G_TRUNC %2(s64)
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%3:_(s64) = COPY $x11
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%1:_(s8) = G_TRUNC %3(s64)
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%4:_(s8) = G_ROTR %0, %1(s8)
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%5:_(s64) = G_ANYEXT %4(s8)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: rotr_i16
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body: |
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bb.1:
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liveins: $x10, $x11
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; CHECK-LABEL: name: rotr_i16
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; CHECK: liveins: $x10, $x11
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]]
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; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]]
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64)
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; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND3]](s64)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[LSHR]], [[SHL]]
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; CHECK-NEXT: $x10 = COPY [[OR]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%2:_(s64) = COPY $x10
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%0:_(s16) = G_TRUNC %2(s64)
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%3:_(s64) = COPY $x11
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%1:_(s16) = G_TRUNC %3(s64)
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%4:_(s16) = G_ROTR %0, %1(s16)
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%5:_(s64) = G_ANYEXT %4(s16)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: rotr_i32
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body: |
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bb.1:
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liveins: $x10, $x11
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; RV64I-LABEL: name: rotr_i32
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
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; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
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; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32
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; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
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; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND]]
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; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]]
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; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND1]]
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; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[SRLW]], [[SLLW]]
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; RV64I-NEXT: $x10 = COPY [[OR]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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;
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; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotr_i32
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; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
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; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
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; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64ZBB_OR_RV64ZBKB-NEXT: [[RORW:%[0-9]+]]:_(s64) = G_RORW [[COPY]], [[COPY1]]
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; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[RORW]](s64)
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; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
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%2:_(s64) = COPY $x10
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%0:_(s32) = G_TRUNC %2(s64)
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%3:_(s64) = COPY $x11
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%1:_(s32) = G_TRUNC %3(s64)
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%4:_(s32) = G_ROTR %0, %1(s32)
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%5:_(s64) = G_ANYEXT %4(s32)
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$x10 = COPY %5(s64)
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PseudoRET implicit $x10
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...
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---
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name: rotr_i64
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body: |
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bb.1:
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liveins: $x10, $x11
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; RV64I-LABEL: name: rotr_i64
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; RV64I: liveins: $x10, $x11
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
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; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
|
|
; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
|
|
; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
|
|
; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s64)
|
|
; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]]
|
|
; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64)
|
|
; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = disjoint G_OR [[LSHR]], [[SHL]]
|
|
; RV64I-NEXT: $x10 = COPY [[OR]](s64)
|
|
; RV64I-NEXT: PseudoRET implicit $x10
|
|
;
|
|
; RV64ZBB_OR_RV64ZBKB-LABEL: name: rotr_i64
|
|
; RV64ZBB_OR_RV64ZBKB: liveins: $x10, $x11
|
|
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
|
|
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
|
|
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
|
|
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s64) = G_ROTR [[COPY]], [[COPY1]](s64)
|
|
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ROTR]](s64)
|
|
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
|
|
%0:_(s64) = COPY $x10
|
|
%1:_(s64) = COPY $x11
|
|
%2:_(s64) = G_ROTR %0, %1(s64)
|
|
$x10 = COPY %2(s64)
|
|
PseudoRET implicit $x10
|
|
|
|
...
|