derek.holloway
7502bf64a4
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389 lines
13 KiB
ArmAsm
389 lines
13 KiB
ArmAsm
// COM: Test all byte_sel values (0-3) for v_cvt_sr_fp8_f32 and v_cvt_f32_fp8
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// COM: with CLAMP=1 (E5M3 mode).
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// COM:
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// COM: Verifies that each byte_sel variant produces the correct byte-merge
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// COM: sequence (SR pack) or byte-extraction sequence (F32 unpack):
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// COM: SR byte_sel=0 -> single v_bfi_b32 merge
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// COM: SR byte_sel=1-3 -> v_lshlrev_b32 + v_bfi_b32 merge
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// COM: Unpack byte_sel=0 -> v_and_b32 (mask 0xFF)
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// COM: Unpack byte_sel=1 -> v_bfe_u32 (offset=8, width=8)
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// COM: Unpack byte_sel=2 -> v_bfe_u32 (offset=16, width=8)
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// COM: Unpack byte_sel=3 -> v_lshrrev_b32 (shift=24)
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// COM:
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// COM: Companion tests:
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// COM: hotswap-cvt-sr-fp8.s - base SR conversion (byte_sel=0 and 2)
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// COM: hotswap-cvt-f32-fp8.s - base unpack conversion (byte_sel=0 and 2)
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// RUN: %clang -target amdgcn-amd-amdhsa -mcpu=gfx1250 -nostdlib %s -o %t.elf
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// RUN: hotswap-rewrite %t.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --dump %t.out.elf --check-idempotent \
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// RUN: | %FileCheck --check-prefix=API %s
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// API: REWRITE: SUCCESS
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// API: IDEMPOTENT: YES
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=SR0 %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=SR1 %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=SR2 %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=SR3 %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=CVT0 %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=CVT1 %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=CVT2 %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=CVT3 %s
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// ---- Kernel 1: SR byte_sel=0 (single v_bfi_b32 merge) ------------------------
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//
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// COM: byte_sel=0 merges via a single v_bfi_b32 (mask 0xFF) with no shift.
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// SR0-LABEL: <test_cvt_sr_fp8_byte0>:
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// SR0: s_branch
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// COM: --- VCC save ---
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// SR0: s_mov_b32
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// SR0-NEXT: v_and_b32{{.*}}0x7fffffff, v1
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// COM: --- High-range direct encode, then final NaN select ---
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// SR0: v_cmp_le_f32{{.*}}0x47800000
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// SR0: v_cndmask_b32
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// COM: --- Byte merge (byte_sel=0: single bfi) ---
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// SR0-NEXT: s_mov_b32
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// SR0-NEXT: v_mov_b32
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// SR0-NEXT: v_cndmask_b32
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// SR0-NEXT: v_bfi_b32 v0,
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// COM: --- VCC restore ---
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// SR0-NEXT: s_mov_b32
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.amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
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.text
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.globl test_cvt_sr_fp8_byte0
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.p2align 8
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.type test_cvt_sr_fp8_byte0,@function
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test_cvt_sr_fp8_byte0:
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v_cvt_sr_fp8_f32 v0, v1, v2 clamp
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s_endpgm
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.Ltest_cvt_sr_fp8_byte0_end:
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.size test_cvt_sr_fp8_byte0, .Ltest_cvt_sr_fp8_byte0_end-test_cvt_sr_fp8_byte0
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// ---- Kernel 2: SR byte_sel=1 (v_lshlrev_b32 + v_bfi_b32 merge) ---------------
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//
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// COM: byte_sel=1 shifts the result byte left by 8 before merging via
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// COM: v_bfi_b32 with mask 0xFF00.
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// SR1-LABEL: <test_cvt_sr_fp8_byte1>:
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// SR1: s_branch
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// COM: --- VCC save + NaN detection (anchor on unique src v4) ---
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// SR1: v_and_b32{{.*}}0x7fffffff, v4
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// COM: --- High-range direct encode, then final NaN select ---
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// SR1: v_cmp_le_f32{{.*}}0x47800000
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// SR1: v_cndmask_b32
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// COM: --- Byte merge (byte_sel=1: shift + bfi) ---
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// SR1-NEXT: s_mov_b32
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// SR1-NEXT: v_mov_b32
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// SR1-NEXT: v_cndmask_b32
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// SR1-NEXT: v_lshlrev_b32
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// SR1-NEXT: v_bfi_b32 v3,
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// COM: --- VCC restore ---
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// SR1-NEXT: s_mov_b32
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.globl test_cvt_sr_fp8_byte1
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.p2align 8
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.type test_cvt_sr_fp8_byte1,@function
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test_cvt_sr_fp8_byte1:
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// v_cvt_sr_fp8_f32 v3, v4, v5 clamp byte_sel=1
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// dword0 = 0xD76BA003 (CLAMP=1, OPSEL[3]=0, OPSEL[2]=1 -> byte_sel=1, vdst=v3)
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// dword1 = 0x02020B04 (src0=v4, src1=v5, no modifiers)
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.long 0xD76BA003
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.long 0x02020B04
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s_endpgm
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.Ltest_cvt_sr_fp8_byte1_end:
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.size test_cvt_sr_fp8_byte1, .Ltest_cvt_sr_fp8_byte1_end-test_cvt_sr_fp8_byte1
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// ---- Kernel 3: SR byte_sel=2 (v_lshlrev_b32 + v_bfi_b32 merge) ---------------
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//
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// COM: byte_sel=2 shifts the result byte left by 16 before merging via
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// COM: v_bfi_b32 with mask 0xFF0000.
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// SR2-LABEL: <test_cvt_sr_fp8_byte2>:
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// SR2: s_branch
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// COM: --- VCC save + NaN detection (anchor on unique src v7) ---
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// SR2: v_and_b32{{.*}}0x7fffffff, v7
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// COM: --- High-range direct encode, then final NaN select ---
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// SR2: v_cmp_le_f32{{.*}}0x47800000
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// SR2: v_cndmask_b32
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// COM: --- Byte merge (byte_sel=2: shift + bfi) ---
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// SR2-NEXT: s_mov_b32
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// SR2-NEXT: v_mov_b32
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// SR2-NEXT: v_cndmask_b32
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// SR2-NEXT: v_lshlrev_b32
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// SR2-NEXT: v_bfi_b32 v6,
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// COM: --- VCC restore ---
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// SR2-NEXT: s_mov_b32
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.globl test_cvt_sr_fp8_byte2
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.p2align 8
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.type test_cvt_sr_fp8_byte2,@function
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test_cvt_sr_fp8_byte2:
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// v_cvt_sr_fp8_f32 v6, v7, v8 clamp byte_sel=2
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// dword0 = 0xD76BC006 (CLAMP=1, OPSEL[3]=1, OPSEL[2]=0 -> byte_sel=2, vdst=v6)
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// dword1 = 0x02021107 (src0=v7, src1=v8, no modifiers)
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.long 0xD76BC006
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.long 0x02021107
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s_endpgm
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.Ltest_cvt_sr_fp8_byte2_end:
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.size test_cvt_sr_fp8_byte2, .Ltest_cvt_sr_fp8_byte2_end-test_cvt_sr_fp8_byte2
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// ---- Kernel 4: SR byte_sel=3 (v_lshlrev_b32 + v_bfi_b32 merge) ---------------
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//
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// COM: byte_sel=3 shifts the result byte left by 24 before merging via
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// COM: v_bfi_b32 with mask 0xFF000000.
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// SR3-LABEL: <test_cvt_sr_fp8_byte3>:
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// SR3: s_branch
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// COM: --- VCC save + NaN detection (anchor on unique src v10) ---
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// SR3: v_and_b32{{.*}}0x7fffffff, v10
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// COM: --- High-range direct encode, then final NaN select ---
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// SR3: v_cmp_le_f32{{.*}}0x47800000
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// SR3: v_cndmask_b32
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// COM: --- Byte merge (byte_sel=3: shift + bfi) ---
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// SR3-NEXT: s_mov_b32
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// SR3-NEXT: v_mov_b32
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// SR3-NEXT: v_cndmask_b32
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// SR3-NEXT: v_lshlrev_b32
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// SR3-NEXT: v_bfi_b32 v9,
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// COM: --- VCC restore ---
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// SR3-NEXT: s_mov_b32
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.globl test_cvt_sr_fp8_byte3
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.p2align 8
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.type test_cvt_sr_fp8_byte3,@function
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test_cvt_sr_fp8_byte3:
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// v_cvt_sr_fp8_f32 v9, v10, v11 clamp byte_sel=3
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// dword0 = 0xD76BE009 (CLAMP=1, OPSEL[3]=1, OPSEL[2]=1 -> byte_sel=3, vdst=v9)
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// dword1 = 0x0202170A (src0=v10, src1=v11, no modifiers)
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.long 0xD76BE009
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.long 0x0202170A
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s_endpgm
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.Ltest_cvt_sr_fp8_byte3_end:
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.size test_cvt_sr_fp8_byte3, .Ltest_cvt_sr_fp8_byte3_end-test_cvt_sr_fp8_byte3
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// ---- Kernel 5: Unpack byte_sel=0 (v_and_b32 extraction) ----------------------
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//
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// COM: byte_sel=0 extracts via v_and_b32 with mask 0xFF.
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// CVT0-LABEL: <test_cvt_f32_fp8_byte0>:
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// CVT0: s_branch
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// COM: --- VCC save + Byte extraction (byte_sel=0: anchor on unique src v1) ---
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// CVT0: v_and_b32{{.*}}0xff, v1
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// COM: --- VCC restore ---
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// CVT0: v_mov_b32{{.*}}0x7fa3d000
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// CVT0-NEXT: v_cndmask_b32{{.*}}v0,
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// CVT0-NEXT: s_mov_b32
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.globl test_cvt_f32_fp8_byte0
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.p2align 8
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.type test_cvt_f32_fp8_byte0,@function
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test_cvt_f32_fp8_byte0:
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v_cvt_f32_fp8 v0, v1 clamp
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s_endpgm
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.Ltest_cvt_f32_fp8_byte0_end:
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.size test_cvt_f32_fp8_byte0, .Ltest_cvt_f32_fp8_byte0_end-test_cvt_f32_fp8_byte0
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// ---- Kernel 6: Unpack byte_sel=1 (v_bfe_u32 extraction) ----------------------
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//
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// COM: byte_sel=1 extracts via v_bfe_u32 with offset=8, width=8.
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// CVT1-LABEL: <test_cvt_f32_fp8_byte1>:
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// CVT1: s_branch
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// COM: --- VCC save + Byte extraction (anchor on unique src v3) ---
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// CVT1: v_bfe_u32{{.*}}v3, 8, 8
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// COM: --- VCC restore ---
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// CVT1: v_mov_b32{{.*}}0x7fa3d000
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// CVT1-NEXT: v_cndmask_b32{{.*}}v2,
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// CVT1-NEXT: s_mov_b32
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.globl test_cvt_f32_fp8_byte1
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.p2align 8
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.type test_cvt_f32_fp8_byte1,@function
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test_cvt_f32_fp8_byte1:
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// v_cvt_f32_fp8 v2, v3 clamp byte_sel=1
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// dword0 = 0xD5EC9002 (CLAMP=1, OPSEL[1]=1 -> byte_sel=1, vdst=v2)
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// dword1 = 0x02010103 (src0=v3, no modifiers)
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.long 0xD5EC9002
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.long 0x02010103
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s_endpgm
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.Ltest_cvt_f32_fp8_byte1_end:
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.size test_cvt_f32_fp8_byte1, .Ltest_cvt_f32_fp8_byte1_end-test_cvt_f32_fp8_byte1
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// ---- Kernel 7: Unpack byte_sel=2 (v_bfe_u32 extraction) ----------------------
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//
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// COM: byte_sel=2 extracts via v_bfe_u32 with offset=16, width=8.
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// CVT2-LABEL: <test_cvt_f32_fp8_byte2>:
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// CVT2: s_branch
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// COM: --- VCC save + Byte extraction (anchor on unique src v5) ---
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// CVT2: v_bfe_u32{{.*}}v5, 16, 8
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// COM: --- VCC restore ---
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// CVT2: v_mov_b32{{.*}}0x7fa3d000
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// CVT2-NEXT: v_cndmask_b32{{.*}}v4,
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// CVT2-NEXT: s_mov_b32
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.globl test_cvt_f32_fp8_byte2
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.p2align 8
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.type test_cvt_f32_fp8_byte2,@function
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test_cvt_f32_fp8_byte2:
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// v_cvt_f32_fp8 v4, v5 clamp byte_sel=2
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// dword0 = 0xD5EC8804 (CLAMP=1, OPSEL[0]=1 -> byte_sel=2, vdst=v4)
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// dword1 = 0x02010105 (src0=v5, no modifiers)
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.long 0xD5EC8804
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.long 0x02010105
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s_endpgm
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.Ltest_cvt_f32_fp8_byte2_end:
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.size test_cvt_f32_fp8_byte2, .Ltest_cvt_f32_fp8_byte2_end-test_cvt_f32_fp8_byte2
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// ---- Kernel 8: Unpack byte_sel=3 (v_lshrrev_b32 extraction) ------------------
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//
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// COM: byte_sel=3 extracts via v_lshrrev_b32 with shift=24.
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// CVT3-LABEL: <test_cvt_f32_fp8_byte3>:
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// CVT3: s_branch
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// COM: --- VCC save + Byte extraction (anchor on unique src v7) ---
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// CVT3: v_lshrrev_b32{{.*}}, 24, v7
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// COM: --- VCC restore ---
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// CVT3: v_mov_b32{{.*}}0x7fa3d000
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// CVT3-NEXT: v_cndmask_b32{{.*}}v6,
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// CVT3-NEXT: s_mov_b32
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.globl test_cvt_f32_fp8_byte3
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.p2align 8
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.type test_cvt_f32_fp8_byte3,@function
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test_cvt_f32_fp8_byte3:
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// v_cvt_f32_fp8 v6, v7 clamp byte_sel=3
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// dword0 = 0xD5EC9806 (CLAMP=1, OPSEL[1]=1, OPSEL[0]=1 -> byte_sel=3, vdst=v6)
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// dword1 = 0x02010107 (src0=v7, no modifiers)
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.long 0xD5EC9806
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.long 0x02010107
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s_endpgm
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.Ltest_cvt_f32_fp8_byte3_end:
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.size test_cvt_f32_fp8_byte3, .Ltest_cvt_f32_fp8_byte3_end-test_cvt_f32_fp8_byte3
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.rodata
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.p2align 8
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.amdhsa_kernel test_cvt_sr_fp8_byte0
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.amdhsa_next_free_vgpr 3
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_sr_fp8_byte1
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.amdhsa_next_free_vgpr 6
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_sr_fp8_byte2
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.amdhsa_next_free_vgpr 9
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_sr_fp8_byte3
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.amdhsa_next_free_vgpr 12
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_f32_fp8_byte0
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.amdhsa_next_free_vgpr 2
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_f32_fp8_byte1
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.amdhsa_next_free_vgpr 4
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_f32_fp8_byte2
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.amdhsa_next_free_vgpr 6
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_f32_fp8_byte3
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.amdhsa_next_free_vgpr 8
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdgpu_metadata
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amdhsa.version:
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- 3
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- 0
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amdhsa.kernels:
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- .name: test_cvt_sr_fp8_byte0
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.symbol: test_cvt_sr_fp8_byte0.kd
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.sgpr_count: 2
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.vgpr_count: 3
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.kernarg_segment_size: 0
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.group_segment_fixed_size: 0
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.private_segment_fixed_size: 0
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.kernarg_segment_align: 8
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.wavefront_size: 64
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.max_flat_workgroup_size: 256
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- .name: test_cvt_sr_fp8_byte1
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.symbol: test_cvt_sr_fp8_byte1.kd
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.sgpr_count: 2
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.vgpr_count: 6
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.kernarg_segment_size: 0
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.group_segment_fixed_size: 0
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|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_sr_fp8_byte2
|
|
.symbol: test_cvt_sr_fp8_byte2.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 9
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_sr_fp8_byte3
|
|
.symbol: test_cvt_sr_fp8_byte3.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 12
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_f32_fp8_byte0
|
|
.symbol: test_cvt_f32_fp8_byte0.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 2
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_f32_fp8_byte1
|
|
.symbol: test_cvt_f32_fp8_byte1.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 4
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_f32_fp8_byte2
|
|
.symbol: test_cvt_f32_fp8_byte2.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 6
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_f32_fp8_byte3
|
|
.symbol: test_cvt_f32_fp8_byte3.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 8
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
.end_amdgpu_metadata
|