derek.holloway
7502bf64a4
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90 lines
2.5 KiB
ArmAsm
90 lines
2.5 KiB
ArmAsm
// COM: Test isSgprLiveAfter edge cases for tensor_load_to_lds patching.
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// COM: A branch instruction between the tensor_load and the next use of
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// COM: the descriptor SGPR forces the heuristic to conservatively assume
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// COM: the SGPR is live, producing save/restore even though the use may
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// COM: not execute on all paths.
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// RUN: %clang -target amdgcn-amd-amdhsa -mcpu=gfx1250 -nostdlib %s -o %t.elf
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// RUN: hotswap-rewrite %t.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --strict-mode --output %t.out.elf \
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// RUN: | %FileCheck --check-prefix=API %s
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// API: RESULT: SUCCESS
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=DISASM %s
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// COM: Kernel 1 (branch guard): s_cbranch_scc1 sits between tensor_load
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// COM: and s_mov (which reads s4). isSgprLiveAfter returns true at the
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// COM: branch, so save/restore is emitted conservatively.
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// DISASM-LABEL: <test_tensor_branch_guard>:
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// DISASM: s_branch
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// DISASM: s_cbranch_scc1
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// DISASM: s_endpgm
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// DISASM: s_mov_b32 [[SCRATCH:s[0-9]+]], s4
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// DISASM-NEXT: s_pack_hh_b32_b16 s4, 0, s4
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// DISASM-NEXT: tensor_load_to_lds
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// DISASM-NEXT: s_mov_b32 s4, [[SCRATCH]]
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// DISASM-NEXT: s_branch
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// COM: Idempotency
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// RUN: hotswap-rewrite %t.out.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --strict-mode --check-idempotent \
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// RUN: | %FileCheck --check-prefix=IDEM %s
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// IDEM: IDEMPOTENT: YES
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.amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
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.text
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.globl test_tensor_branch_guard
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.p2align 8
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.type test_tensor_branch_guard,@function
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test_tensor_branch_guard:
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tensor_load_to_lds s[0:3], s[4:11]
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s_cbranch_scc1 .Lskip
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s_mov_b32 s0, s4
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.Lskip:
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s_endpgm
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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s_nop 0
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.Ltest_tensor_branch_guard_end:
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.size test_tensor_branch_guard, .Ltest_tensor_branch_guard_end-test_tensor_branch_guard
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.rodata
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.p2align 8
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.amdhsa_kernel test_tensor_branch_guard
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.amdhsa_next_free_vgpr 1
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.amdhsa_next_free_sgpr 12
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.end_amdhsa_kernel
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.amdgpu_metadata
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amdhsa.version:
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- 3
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- 0
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amdhsa.kernels:
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- .name: test_tensor_branch_guard
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.symbol: test_tensor_branch_guard.kd
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.sgpr_count: 12
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.vgpr_count: 1
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.kernarg_segment_size: 0
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.group_segment_fixed_size: 0
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.private_segment_fixed_size: 0
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.kernarg_segment_align: 8
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.wavefront_size: 64
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.max_flat_workgroup_size: 256
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.end_amdgpu_metadata
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