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102 lines
3.5 KiB
ArmAsm
102 lines
3.5 KiB
ArmAsm
// COM: Verify that hotswap rejects an optional VGPR bump which would make a
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// COM: maximum-size workgroup unschedulable, while applying the same patch
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// COM: when the kernel has occupancy headroom. Also verify that an applied
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// COM: bump updates runtime-visible .vgpr_count metadata.
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// RUN: %clang -target amdgcn-amd-amdhsa -mcpu=gfx1250 -nostdlib %s -o %t.elf
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// RUN: env AMD_COMGR_EMIT_VERBOSE_LOGS=1 hotswap-rewrite %t.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --output %t.out.elf 2>&1 | %FileCheck --check-prefix=LOG %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=DISASM %s
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// RUN: %llvm-readelf --notes %t.out.elf | %FileCheck --check-prefix=META %s
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// LOG: optional patch for kernel 'capacity_limited' would grow VGPRs from 128 to 129 and reduce capacity to 7 waves/EU, below the 8 waves/EU needed for one maximum-size workgroup; declining patch.
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// LOG: RESULT: SUCCESS
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// DISASM-LABEL: <capacity_limited>:
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// DISASM-NEXT: ds_store_addtid_b32 v127
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// DISASM-LABEL: <has_headroom>:
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// DISASM-NOT: ds_store_addtid_b32
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// DISASM: s_branch
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// DISASM: ds_store_b32 v16, v15
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// META: .name: capacity_limited
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// META: .vgpr_count: 128
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// META: .name: has_headroom
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// META: .vgpr_count: 17
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.amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
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.text
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.globl capacity_limited
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.p2align 8
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.type capacity_limited,@function
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capacity_limited:
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ds_store_addtid_b32 v127
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.irp reg,v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,v10,v11,v12,v13,v14,v15,v16,v17,v18,v19,v20,v21,v22,v23,v24,v25,v26,v27,v28,v29,v30,v31
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v_cmp_eq_u32 vcc_lo, \reg, \reg
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.endr
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.irp reg,v32,v33,v34,v35,v36,v37,v38,v39,v40,v41,v42,v43,v44,v45,v46,v47,v48,v49,v50,v51,v52,v53,v54,v55,v56,v57,v58,v59,v60,v61,v62,v63
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v_cmp_eq_u32 vcc_lo, \reg, \reg
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.endr
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.irp reg,v64,v65,v66,v67,v68,v69,v70,v71,v72,v73,v74,v75,v76,v77,v78,v79,v80,v81,v82,v83,v84,v85,v86,v87,v88,v89,v90,v91,v92,v93,v94,v95
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v_cmp_eq_u32 vcc_lo, \reg, \reg
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.endr
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.irp reg,v96,v97,v98,v99,v100,v101,v102,v103,v104,v105,v106,v107,v108,v109,v110,v111,v112,v113,v114,v115,v116,v117,v118,v119,v120,v121,v122,v123,v124,v125,v126,v127
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v_cmp_eq_u32 vcc_lo, \reg, \reg
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.endr
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s_endpgm
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.Lcapacity_limited_end:
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.size capacity_limited, .Lcapacity_limited_end-capacity_limited
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.globl has_headroom
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.p2align 8
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.type has_headroom,@function
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has_headroom:
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ds_store_addtid_b32 v15
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.irp reg,v0,v1,v2,v3,v4,v5,v6,v7,v8,v9,v10,v11,v12,v13,v14,v15
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v_cmp_eq_u32 vcc_lo, \reg, \reg
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.endr
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s_endpgm
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.Lhas_headroom_end:
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.size has_headroom, .Lhas_headroom_end-has_headroom
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.rodata
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.p2align 8
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.amdhsa_kernel capacity_limited
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.amdhsa_next_free_vgpr 128
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.amdhsa_next_free_sgpr 2
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.amdhsa_wavefront_size32 1
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.end_amdhsa_kernel
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.amdhsa_kernel has_headroom
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.amdhsa_next_free_vgpr 16
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.amdhsa_next_free_sgpr 2
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.amdhsa_wavefront_size32 1
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.end_amdhsa_kernel
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.amdgpu_metadata
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amdhsa.version:
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- 3
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- 0
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amdhsa.kernels:
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- .name: capacity_limited
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.symbol: capacity_limited.kd
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.sgpr_count: 2
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.vgpr_count: 128
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.kernarg_segment_size: 0
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.group_segment_fixed_size: 0
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.private_segment_fixed_size: 0
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.kernarg_segment_align: 8
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.wavefront_size: 32
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.max_flat_workgroup_size: 1024
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- .name: has_headroom
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.symbol: has_headroom.kd
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.sgpr_count: 2
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.vgpr_count: 16
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.kernarg_segment_size: 0
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.group_segment_fixed_size: 0
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.private_segment_fixed_size: 0
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.kernarg_segment_align: 8
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.wavefront_size: 32
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.max_flat_workgroup_size: 256
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.end_amdgpu_metadata
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