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94 lines
4.3 KiB
ArmAsm
94 lines
4.3 KiB
ArmAsm
// A kernel may allocate more than 256 physical VGPRs through gfx1250's
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// VGPR-MSB mode. The scale16 lowering's generated assembly must still use
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// encodable v0-v255 names and select its above-KD scratch bank explicitly.
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// The bump is occupancy-neutral (the original and rewritten allocations both
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// admit one wave/EU), despite the maximum-workgroup metadata asking for two.
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// RUN: %clang -target amdgcn-amd-amdhsa -mcpu=gfx1250 -nostdlib %s -o %t.elf
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// RUN: env AMD_COMGR_EMIT_VERBOSE_LOGS=1 hotswap-rewrite %t.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --output %t.out.elf 2>&1 | %FileCheck --check-prefix=API %s
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// API: wmma_scale16: exact K-split
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// API-NOT: register index is out of range
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// API-NOT: error:
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// API: RESULT: SUCCESS
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=DISASM %s
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// DISASM-LABEL: <test_wmma_scale16_large_vgpr_count>:
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// DISASM-NOT: v_wmma_scale16
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// COM: Masked A and generated scale operands share a preserved bank-zero
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// COM: block. Matrix B remains in above-KD scratch. Each WMMA consumes the
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// COM: exact low-bank values produced by its gather.
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// DISASM: v_and_b32_e32 [[LO_A:v[0-9]+]], 0xff, v0{{[[:space:]]+//}}
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// DISASM: v_and_b32_e32 [[LO_B:v[0-9]+]], 0xff, v18{{[[:space:]]+//}}
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// DISASM: v_bfe_u32 [[HI_A:v[0-9]+]], v0, 8, 8
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// DISASM: v_bfe_u32 [[HI_B:v[0-9]+]], v18, 8, 8
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// DISASM: v_lshl_or_b32 [[HI_B]], {{.*}}, 24, [[HI_B]]
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// DISASM-NEXT: s_wait_xcnt 0x0
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// DISASM-NEXT: s_set_vgpr_msb {{.*}}
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// DISASM-NEXT: v_wmma_scale_f32_16x16x128_f8f6f4 v[38:45], v[2:9], v[190:197] /*v[702:709]*/, 0, [[LO_A]], [[LO_B]]
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// DISASM: v_mov_b32_e32 v9, v181
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// DISASM-NEXT: v_wmma_scale_f32_16x16x128_f8f6f4 v[38:45], v[2:9], v[190:197] /*v[702:709]*/, v[38:45], [[HI_A]], [[HI_B]]
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// DISASM-NEXT: v_nop
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// DISASM-NEXT: s_wait_xcnt 0x0
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// DISASM-NEXT: s_set_vgpr_msb 0x80a
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// DISASM-NEXT: v_mov_b32_e32 v2, v176 /*v688*/
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// DISASM: v_and_b32_e32 [[LO_A_2:v[0-9]+]], 0xff, v0{{[[:space:]]+//}}
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// DISASM: v_and_b32_e32 [[LO_B_2:v[0-9]+]], 0xff, v18{{[[:space:]]+//}}
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// DISASM: v_bfe_u32 [[HI_A_2:v[0-9]+]], v0, 8, 8
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// DISASM: v_bfe_u32 [[HI_B_2:v[0-9]+]], v18, 8, 8
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// DISASM: v_wmma_scale_f32_16x16x128_f8f6f4 v[38:45], v[2:9], v[190:197] /*v[702:709]*/, 0, [[LO_A_2]], [[LO_B_2]]
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// DISASM: v_mov_b32_e32 v9, v181
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// DISASM-NEXT: v_wmma_scale_f32_16x16x128_f8f6f4 v[38:45], v[2:9], v[190:197] /*v[702:709]*/, v[38:45], [[HI_A_2]], [[HI_B_2]]
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// DISASM-NEXT: v_nop
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// DISASM-NEXT: s_wait_xcnt 0x0
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// DISASM-NEXT: s_set_vgpr_msb 0x80a
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// DISASM-NEXT: v_mov_b32_e32 v2, v176 /*v688*/
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// DISASM: v_mov_b32_e32 v14, v188 /*v700*/
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// DISASM-NEXT: s_wait_xcnt 0x0
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// DISASM-NEXT: s_set_vgpr_msb 0xa00
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// RUN: hotswap-rewrite %t.out.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --check-idempotent | %FileCheck --check-prefix=IDEM %s
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// IDEM: IDEMPOTENT: YES
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.amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
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.text
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.globl test_wmma_scale16_large_vgpr_count
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.p2align 8
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.type test_wmma_scale16_large_vgpr_count,@function
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test_wmma_scale16_large_vgpr_count:
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s_set_vgpr_msb 0x100
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v_mov_b32 v10, v10
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v_wmma_scale16_f32_16x16x128_f8f6f4 v[38:45], v[174:181], v[254:261], 0, v[0:1], v[18:19] matrix_a_fmt:MATRIX_FMT_FP4 matrix_b_fmt:MATRIX_FMT_FP4 matrix_a_scale_fmt:MATRIX_SCALE_FMT_E4M3 matrix_b_scale_fmt:MATRIX_SCALE_FMT_E4M3
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v_wmma_scale16_f32_16x16x128_f8f6f4 v[38:45], v[174:181], v[240:247], 0, v[0:1], v[18:19] matrix_a_fmt:MATRIX_FMT_FP4 matrix_b_fmt:MATRIX_FMT_FP4 matrix_a_scale_fmt:MATRIX_SCALE_FMT_E4M3 matrix_b_scale_fmt:MATRIX_SCALE_FMT_E4M3
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s_endpgm
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.Ltest_wmma_scale16_large_vgpr_count_end:
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.size test_wmma_scale16_large_vgpr_count, .Ltest_wmma_scale16_large_vgpr_count_end-test_wmma_scale16_large_vgpr_count
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.rodata
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.p2align 8
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.amdhsa_kernel test_wmma_scale16_large_vgpr_count
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.amdhsa_next_free_vgpr 688
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.amdhsa_next_free_sgpr 2
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.amdhsa_wavefront_size32 1
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.end_amdhsa_kernel
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.amdgpu_metadata
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amdhsa.version:
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- 3
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- 0
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amdhsa.kernels:
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- .name: test_wmma_scale16_large_vgpr_count
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.symbol: test_wmma_scale16_large_vgpr_count.kd
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.sgpr_count: 2
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.vgpr_count: 688
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.kernarg_segment_size: 0
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.group_segment_fixed_size: 0
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.private_segment_fixed_size: 0
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.kernarg_segment_align: 8
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.wavefront_size: 32
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.max_flat_workgroup_size: 256
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.end_amdgpu_metadata
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