derek.holloway
7502bf64a4
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84 lines
3.1 KiB
ArmAsm
84 lines
3.1 KiB
ArmAsm
// Recover exact VGPR-MSB state through CFG joins instead of rejecting every
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// direct target. This covers a backedge loop, a nonzero fixed point, and a
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// non-MODE SETREG that must preserve the tracked fields.
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// RUN: %clang -target amdgcn-amd-amdhsa -mcpu=gfx1250 -nostdlib %s -o %t.elf
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// RUN: env AMD_COMGR_EMIT_VERBOSE_LOGS=1 hotswap-rewrite %t.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250:gfx1250-b0-specific+ \
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// RUN: amdgcn-amd-amdhsa--gfx1250:gfx1250-b0-specific- \
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// RUN: --output %t.out.elf 2>&1 | %FileCheck --check-prefix=API %s
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// API-COUNT-3: WMMA split: patched v_wmma_f32_16x16x128_fp8_fp8
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// API-NOT: error:
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// API: RESULT: SUCCESS
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=DISASM %s
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// DISASM-LABEL: <test_wmma_zero_loop>:
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// DISASM: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
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// DISASM: s_branch
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// DISASM: s_cbranch_scc1
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// DISASM-LABEL: <test_wmma_nonzero_loop>:
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// DISASM: s_set_vgpr_msb 0x60
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// DISASM: s_branch
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// DISASM: s_cbranch_scc1
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// DISASM-LABEL: <test_wmma_nonmode_setreg>:
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// DISASM: s_set_vgpr_msb 0x60
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// DISASM-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_STATUS), 7
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// DISASM-NEXT: s_branch
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// DISASM: Disassembly of section :
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// DISASM: v_wmma_f32_16x16x64_fp8_fp8
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// DISASM-NEXT: v_wmma_f32_16x16x64_fp8_fp8
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// DISASM-NEXT: s_branch
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// DISASM-NEXT: v_wmma_f32_16x16x64_fp8_fp8
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// DISASM-NEXT: s_set_vgpr_msb 0x6050
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// DISASM-NEXT: v_wmma_f32_16x16x64_fp8_fp8
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// DISASM-NEXT: s_set_vgpr_msb 0x5060
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// DISASM-NEXT: s_branch
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// DISASM-NEXT: v_wmma_f32_16x16x64_fp8_fp8
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// DISASM-NEXT: s_set_vgpr_msb 0x6050
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// DISASM-NEXT: v_wmma_f32_16x16x64_fp8_fp8
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// DISASM-NEXT: s_set_vgpr_msb 0x5060
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// DISASM-NEXT: s_branch
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// RUN: hotswap-rewrite %t.out.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250:gfx1250-b0-specific- \
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// RUN: amdgcn-amd-amdhsa--gfx1250:gfx1250-b0-specific- \
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// RUN: --check-idempotent | %FileCheck --check-prefix=IDEM %s
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// IDEM: IDEMPOTENT: YES
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.amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
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.text
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.globl test_wmma_zero_loop
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.p2align 8
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.type test_wmma_zero_loop,@function
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test_wmma_zero_loop:
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// gfx1250's SETREG fixup writes VGPR-MSB fields from imm32[19:12], which
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// are zero here even though the selected WAVE_MODE bit is set to one.
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s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
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.Lzero_loop:
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v_wmma_f32_16x16x128_fp8_fp8 v[32:39], v[0:15], v[16:31], 0
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s_cbranch_scc1 .Lzero_loop
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s_endpgm
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.size test_wmma_zero_loop, .-test_wmma_zero_loop
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.globl test_wmma_nonzero_loop
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.p2align 8
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.type test_wmma_nonzero_loop,@function
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test_wmma_nonzero_loop:
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s_set_vgpr_msb 0x60
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.Lnonzero_loop:
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v_wmma_f32_16x16x128_fp8_fp8 v[32:39], v[0:15], v[16:31], 0
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s_cbranch_scc1 .Lnonzero_loop
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s_endpgm
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.size test_wmma_nonzero_loop, .-test_wmma_nonzero_loop
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.globl test_wmma_nonmode_setreg
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.p2align 8
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.type test_wmma_nonmode_setreg,@function
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test_wmma_nonmode_setreg:
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s_set_vgpr_msb 0x60
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s_setreg_imm32_b32 hwreg(HW_REG_WAVE_STATUS), 7
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v_wmma_f32_16x16x128_fp8_fp8 v[32:39], v[0:15], v[16:31], 0
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s_endpgm
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.size test_wmma_nonmode_setreg, .-test_wmma_nonmode_setreg
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