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114 lines
3.5 KiB
ArmAsm
114 lines
3.5 KiB
ArmAsm
// Table coverage: exercise every entry in the WMMA split table through the
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// VGPR-MSB-aware split + bracket path. Each kernel holds one splittable opcode
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// whose upper source half crosses v255, so the split runs and brackets the
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// crossing half. The per-SplitKind bracket bytes are checked in detail by
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// hotswap-wmma-split-vgpr-msb.s (Split128to64FP8BF8) and
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// hotswap-wmma-split-vgpr-msb-m-roles.s (Split32x16to16x16F4); this test
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// guarantees no table entry is left unsplit.
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// RUN: %clang -target amdgcn-amd-amdhsa -mcpu=gfx1250 -nostdlib %s -o %t.elf
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// RUN: env AMD_COMGR_EMIT_VERBOSE_LOGS=1 hotswap-rewrite %t.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --output %t.out.elf 2>&1 | %FileCheck --check-prefix=API %s
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// API-NOT: error:
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// API: WMMA split: patched v_wmma_f16_16x16x128_fp8_fp8
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// API: WMMA split: patched v_wmma_f16_16x16x128_fp8_bf8
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// API: WMMA split: patched v_wmma_f16_16x16x128_bf8_fp8
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// API: WMMA split: patched v_wmma_f16_16x16x128_bf8_bf8
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// API: WMMA split: patched v_wmma_f32_16x16x128_fp8_fp8
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// API: WMMA split: patched v_wmma_f32_16x16x128_fp8_bf8
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// API: WMMA split: patched v_wmma_f32_16x16x128_bf8_fp8
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// API: WMMA split: patched v_wmma_f32_16x16x128_bf8_bf8
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// API: WMMA split: patched v_wmma_f32_32x16x128_f4
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// API: RESULT: SUCCESS
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// A second rewrite must be byte-identical.
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// RUN: hotswap-rewrite %t.out.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --check-idempotent | %FileCheck --check-prefix=IDEM %s
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// IDEM: IDEMPOTENT: YES
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.amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
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.text
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.globl k_f16_fp8_fp8
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.p2align 8
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.type k_f16_fp8_fp8,@function
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k_f16_fp8_fp8:
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s_set_vgpr_msb 0
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v_wmma_f16_16x16x128_fp8_fp8 v[16:19], v[250:265], v[100:115], v[16:19]
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s_endpgm
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.size k_f16_fp8_fp8, .-k_f16_fp8_fp8
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.globl k_f16_fp8_bf8
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.p2align 8
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.type k_f16_fp8_bf8,@function
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k_f16_fp8_bf8:
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s_set_vgpr_msb 0
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v_wmma_f16_16x16x128_fp8_bf8 v[16:19], v[250:265], v[100:115], v[16:19]
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s_endpgm
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.size k_f16_fp8_bf8, .-k_f16_fp8_bf8
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.globl k_f16_bf8_fp8
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.p2align 8
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.type k_f16_bf8_fp8,@function
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k_f16_bf8_fp8:
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s_set_vgpr_msb 0
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v_wmma_f16_16x16x128_bf8_fp8 v[16:19], v[250:265], v[100:115], v[16:19]
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s_endpgm
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.size k_f16_bf8_fp8, .-k_f16_bf8_fp8
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.globl k_f16_bf8_bf8
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.p2align 8
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.type k_f16_bf8_bf8,@function
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k_f16_bf8_bf8:
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s_set_vgpr_msb 0
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v_wmma_f16_16x16x128_bf8_bf8 v[16:19], v[250:265], v[100:115], v[16:19]
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s_endpgm
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.size k_f16_bf8_bf8, .-k_f16_bf8_bf8
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.globl k_f32_fp8_fp8
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.p2align 8
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.type k_f32_fp8_fp8,@function
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k_f32_fp8_fp8:
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s_set_vgpr_msb 0
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v_wmma_f32_16x16x128_fp8_fp8 v[16:23], v[250:265], v[100:115], v[16:23]
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s_endpgm
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.size k_f32_fp8_fp8, .-k_f32_fp8_fp8
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.globl k_f32_fp8_bf8
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.p2align 8
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.type k_f32_fp8_bf8,@function
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k_f32_fp8_bf8:
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s_set_vgpr_msb 0
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v_wmma_f32_16x16x128_fp8_bf8 v[16:23], v[250:265], v[100:115], v[16:23]
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s_endpgm
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.size k_f32_fp8_bf8, .-k_f32_fp8_bf8
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.globl k_f32_bf8_fp8
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.p2align 8
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.type k_f32_bf8_fp8,@function
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k_f32_bf8_fp8:
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s_set_vgpr_msb 0
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v_wmma_f32_16x16x128_bf8_fp8 v[16:23], v[250:265], v[100:115], v[16:23]
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s_endpgm
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.size k_f32_bf8_fp8, .-k_f32_bf8_fp8
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.globl k_f32_bf8_bf8
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.p2align 8
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.type k_f32_bf8_bf8,@function
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k_f32_bf8_bf8:
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s_set_vgpr_msb 0
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v_wmma_f32_16x16x128_bf8_bf8 v[16:23], v[250:265], v[100:115], v[16:23]
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s_endpgm
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.size k_f32_bf8_bf8, .-k_f32_bf8_bf8
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.globl k_f32_32x16x128_f4
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.p2align 8
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.type k_f32_32x16x128_f4,@function
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k_f32_32x16x128_f4:
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s_set_vgpr_msb 0
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v_wmma_f32_32x16x128_f4 v[250:265], v[248:263], v[100:107], v[252:267]
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s_endpgm
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.size k_f32_32x16x128_f4, .-k_f32_32x16x128_f4
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