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188 lines
5.3 KiB
ArmAsm
188 lines
5.3 KiB
ArmAsm
; Kernel test3_v2 wth printf, code-object-v2 source
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.text
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.hsa_code_object_version 2,1
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.hsa_code_object_isa 8,0,3,"AMD","AMDGPU"
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.protected test3_v2 ; -- Begin function test3_v2
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.globl test3_v2
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.p2align 8
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.type test3_v2,@function
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.amdgpu_hsa_kernel test3_v2
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test3_v2: ; @test3_v2
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test3_v2$local:
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.amd_kernel_code_t
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amd_code_version_major = 1
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amd_code_version_minor = 2
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amd_machine_kind = 1
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amd_machine_version_major = 8
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amd_machine_version_minor = 0
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amd_machine_version_stepping = 3
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kernel_code_entry_byte_offset = 256
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kernel_code_prefetch_byte_size = 0
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granulated_workitem_vgpr_count = 5
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granulated_wavefront_sgpr_count = 5
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priority = 0
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float_mode = 192
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priv = 0
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enable_dx10_clamp = 1
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debug_mode = 0
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enable_ieee_mode = 1
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enable_wgp_mode = 0
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enable_mem_ordered = 0
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enable_fwd_progress = 0
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enable_sgpr_private_segment_wave_byte_offset = 1
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user_sgpr_count = 6
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enable_trap_handler = 0
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enable_sgpr_workgroup_id_x = 1
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enable_sgpr_workgroup_id_y = 0
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enable_sgpr_workgroup_id_z = 0
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enable_sgpr_workgroup_info = 0
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enable_vgpr_workitem_id = 0
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enable_exception_msb = 0
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granulated_lds_size = 0
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enable_exception = 0
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enable_sgpr_private_segment_buffer = 1
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enable_sgpr_dispatch_ptr = 0
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enable_sgpr_queue_ptr = 0
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enable_sgpr_kernarg_segment_ptr = 0
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enable_sgpr_dispatch_id = 0
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enable_sgpr_flat_scratch_init = 1
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enable_sgpr_private_segment_size = 0
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enable_sgpr_grid_workgroup_count_x = 0
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enable_sgpr_grid_workgroup_count_y = 0
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enable_sgpr_grid_workgroup_count_z = 0
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enable_wavefront_size32 = 0
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enable_ordered_append_gds = 0
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private_element_size = 1
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is_ptr64 = 1
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is_dynamic_callstack = 1
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is_debug_enabled = 0
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is_xnack_enabled = 0
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workitem_private_segment_byte_size = 16384
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workgroup_group_segment_byte_size = 0
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gds_segment_byte_size = 0
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kernarg_segment_byte_size = 56
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workgroup_fbarrier_count = 0
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wavefront_sgpr_count = 48
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workitem_vgpr_count = 24
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reserved_vgpr_first = 0
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reserved_vgpr_count = 0
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reserved_sgpr_first = 0
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reserved_sgpr_count = 0
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debug_wavefront_private_segment_offset_sgpr = 0
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debug_private_segment_buffer_sgpr = 0
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kernarg_segment_alignment = 4
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group_segment_alignment = 4
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private_segment_alignment = 4
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wavefront_size = 6
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call_convention = -1
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runtime_loader_kernel_symbol = 0
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.end_amd_kernel_code_t
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; %bb.0: ; %entry
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s_add_u32 s4, s4, s7
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s_lshr_b32 flat_scratch_hi, s4, 8
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s_add_u32 s0, s0, s7
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s_addc_u32 s1, s1, 0
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s_mov_b32 flat_scratch_lo, s5
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s_getpc_b64 s[4:5]
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s_add_u32 s4, s4, __printf_alloc@gotpcrel32@lo+4
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s_addc_u32 s5, s5, __printf_alloc@gotpcrel32@hi+4
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s_load_dwordx2 s[4:5], s[4:5], 0x0
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v_mov_b32_e32 v0, 4
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s_mov_b32 s32, 0
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s_mov_b32 s33, 0
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s_waitcnt lgkmcnt(0)
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s_swappc_b64 s[30:31], s[4:5]
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v_cmp_ne_u64_e32 vcc, 0, v[0:1]
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s_and_saveexec_b64 s[4:5], vcc
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s_cbranch_execz BB0_2
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; %bb.1:
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v_mov_b32_e32 v2, 1
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flat_store_dword v[0:1], v2
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BB0_2:
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s_endpgm
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.Lfunc_end0:
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.size test3_v2, .Lfunc_end0-test3_v2
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; -- End function
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.section .AMDGPU.csdata
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; Kernel info:
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; codeLenInByte = 96
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; NumSgprs: 48
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; NumVgprs: 24
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; ScratchSize: 16384
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; MemoryBound: 0
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; FloatMode: 192
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; IeeeMode: 1
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; LDSByteSize: 0 bytes/workgroup (compile time only)
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; SGPRBlocks: 5
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; VGPRBlocks: 5
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; NumSGPRsForWavesPerEU: 48
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; NumVGPRsForWavesPerEU: 24
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; Occupancy: 10
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; WaveLimiterHint : 0
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; COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
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; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
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; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
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; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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.ident "clang version 11.0.0 (https://github.com/llvm/llvm-project.git 20629ca949cddde9f7e41a4b9e8539a970615feb)"
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.section ".note.GNU-stack"
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.addrsig
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.amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx803"
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.amd_amdgpu_hsa_metadata
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---
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Version: [ 1, 0 ]
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Printf:
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- '1:0:foo'
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Kernels:
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- Name: test3_v2
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SymbolName: 'test3_v2@kd'
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Language: OpenCL C
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LanguageVersion: [ 2, 0 ]
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Args:
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- Size: 8
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Align: 8
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ValueKind: HiddenGlobalOffsetX
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ValueType: I64
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- Size: 8
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Align: 8
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ValueKind: HiddenGlobalOffsetY
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ValueType: I64
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- Size: 8
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Align: 8
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ValueKind: HiddenGlobalOffsetZ
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ValueType: I64
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- Size: 8
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Align: 8
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ValueKind: HiddenPrintfBuffer
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ValueType: I8
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AddrSpaceQual: Global
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- Size: 8
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Align: 8
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ValueKind: HiddenNone
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ValueType: I8
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AddrSpaceQual: Global
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- Size: 8
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Align: 8
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ValueKind: HiddenNone
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ValueType: I8
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AddrSpaceQual: Global
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- Size: 8
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Align: 8
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ValueKind: HiddenMultiGridSyncArg
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ValueType: I8
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AddrSpaceQual: Global
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CodeProps:
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KernargSegmentSize: 56
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GroupSegmentFixedSize: 0
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PrivateSegmentFixedSize: 16384
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KernargSegmentAlign: 4
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WavefrontSize: 64
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NumSGPRs: 48
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NumVGPRs: 24
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MaxFlatWorkGroupSize: 256
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IsDynamicCallStack: true
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...
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.end_amd_amdgpu_hsa_metadata
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