derek.holloway
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59 lines
2.0 KiB
ArmAsm
59 lines
2.0 KiB
ArmAsm
## This checks that shrink wrapping does not pessimize a CFG pattern where two
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## blocks can be proved to have the same execution count but, because of profile
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## inaccuricies, we could move saves into the second block. We can prove two
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## blocks have the same frequency when B post-dominate A and A dominates B and
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## are at the same loop nesting level. This would be a pessimization because
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## shrink wrapping is unlikely to be able to cleanly move PUSH instructions,
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## inserting additional store instructions.
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# REQUIRES: system-linux
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# RUN: llvm-mc -filetype=obj -triple x86_64-unknown-unknown \
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# RUN: %s -o %t.o
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# RUN: link_fdata %s %t.o %t.fdata
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# RUN: llvm-strip --strip-unneeded %t.o
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# RUN: %clang %cflags %t.o -o %t.exe -Wl,-q -nostdlib
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# RUN: llvm-bolt -relocs %t.exe -o %t.out -data %t.fdata \
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# RUN: -frame-opt=all -equalize-bb-counts | FileCheck %s
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## Here we create a CFG pattern with two blocks A and B belonging to the same
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## equivalency class as defined by dominance relations and having in theory
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## the same frequency. But we tweak edge counts from profile to make block A
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## hotter than block B.
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.globl _start
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.type _start, %function
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_start:
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.cfi_startproc
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## Hot prologue
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# FDATA: 0 [unknown] 0 1 _start 0 0 10
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push %rbp
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mov %rsp, %rbp
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push %rbx
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push %r14
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subq $0x20, %rsp
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b: je end_if_1
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# FDATA: 1 _start #b# 1 _start #end_if_1# 0 1
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if_false:
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movq rel(%rip), %rdi # Add this to create a relocation and run bolt w/ relocs
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c: jmp end_if_1
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## Reduce frequency from 9 to 1 to simulate an inaccurate profile
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# FDATA: 1 _start #c# 1 _start #end_if_1# 0 1
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end_if_1:
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# first uses of R14 and RBX appear at this point, possible move point for SW
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mov %r14, %rdi
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mov %rbx, %rdi
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leaq -0x20(%rbp), %r14
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movq -0x20(%rbp), %rdi
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addq $0x20, %rsp
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pop %r14
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pop %rbx
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pop %rbp
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ret
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.cfi_endproc
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.size _start, .-_start
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.data
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rel: .quad _start
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# CHECK: BOLT-INFO: Shrink wrapping moved 0 spills inserting load/stores and 0 spills inserting push/pops
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