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16 lines
661 B
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.. title:: clang-tidy - altera-kernel-name-restriction
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altera-kernel-name-restriction
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==============================
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Finds kernel files and include directives whose filename is `kernel.cl`,
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`Verilog.cl`, or `VHDL.cl`. The check is case insensitive.
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Such kernel file names cause the offline compiler to generate intermediate
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design files that have the same names as certain internal files, which
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leads to a compilation error.
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Based on the `Guidelines for Naming the Kernel` section in the
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`Intel FPGA SDK for OpenCL Pro Edition: Programming Guide
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<https://www.intel.com/content/www/us/en/programmable/documentation/mwh1391807965224.html#ewa1412973930963>`_.
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