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56 lines
3.6 KiB
C++
56 lines
3.6 KiB
C++
// RUN: %check_clang_tidy %s altera-kernel-name-restriction %t -- -- -I%S/Inputs/kernel-name-restriction
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// RUN: %check_clang_tidy -check-suffix=UPPERCASE %s altera-kernel-name-restriction %t -- -- -I%S/Inputs/kernel-name-restriction/uppercase -DUPPERCASE
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#ifdef UPPERCASE
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// The warning should be triggered regardless of capitalization
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#include "KERNEL.cl"
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// CHECK-MESSAGES-UPPERCASE: :[[@LINE-1]]:1: warning: including 'KERNEL.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]
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#include "vERILOG.cl"
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// CHECK-MESSAGES-UPPERCASE: :[[@LINE-1]]:1: warning: including 'vERILOG.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]
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#include "VHDL.cl"
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// CHECK-MESSAGES-UPPERCASE: :[[@LINE-1]]:1: warning: including 'VHDL.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]
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#else
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// These are the banned kernel filenames, and should trigger warnings
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#include "kernel.cl"
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// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'kernel.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]
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#include "Verilog.cl"
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// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'Verilog.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]
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#include "vhdl.CL"
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// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'vhdl.CL' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]
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// The warning should be triggered if the names are within a directory
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#include "some/dir/kernel.cl"
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// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'kernel.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]
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#include "somedir/verilog.cl"
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// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'verilog.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]
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#include "otherdir/vhdl.cl"
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// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: including 'vhdl.cl' may cause additional compilation errors due to the name of the kernel source file; consider renaming the included kernel source file [altera-kernel-name-restriction]
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// There are no FIX-ITs for the altera-kernel-name-restriction lint check
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// The following include directives shouldn't trigger the warning
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#include "otherthing.cl"
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#include "thing.h"
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// It doesn't make sense to have kernel.h, verilog.h, or vhdl.h as filenames
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// without the corresponding .cl files, but the Altera Programming Guide doesn't
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// explicitly forbid it.
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#include "kernel.h"
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#include "verilog.h"
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#include "vhdl.h"
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// The files can still have the forbidden names in them, so long as they're not
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// the entire file name, and are not the kernel source file name.
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#include "some_kernel.cl"
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#include "other_Verilog.cl"
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#include "vhdl_number_two.cl"
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// Naming a directory kernel.cl, verilog.cl, or vhdl.cl is not explicitly
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// forbidden in the Altera Programming Guide either.
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#include "some/kernel.cl/foo.h"
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#include "some/verilog.cl/foo.h"
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#include "some/vhdl.cl/foo.h"
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#endif
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