derek.holloway
7502bf64a4
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976 lines
48 KiB
C++
976 lines
48 KiB
C++
/*===--- __clang_cuda_intrinsics.h - Device-side CUDA intrinsic wrappers ---===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __CLANG_CUDA_INTRINSICS_H__
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#define __CLANG_CUDA_INTRINSICS_H__
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#ifndef __CUDA__
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#error "This file is for CUDA compilation only."
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#endif
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// sm_30 intrinsics: __shfl_{up,down,xor}.
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#define __SM_30_INTRINSICS_H__
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#define __SM_30_INTRINSICS_HPP__
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#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 300
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#pragma push_macro("__MAKE_SHUFFLES")
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#define __MAKE_SHUFFLES(__FnName, __IntIntrinsic, __FloatIntrinsic, __Mask, \
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__Type) \
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inline __device__ int __FnName(int __val, __Type __offset, \
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int __width = warpSize) { \
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return __IntIntrinsic(__val, __offset, \
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((warpSize - __width) << 8) | (__Mask)); \
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} \
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inline __device__ float __FnName(float __val, __Type __offset, \
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int __width = warpSize) { \
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return __FloatIntrinsic(__val, __offset, \
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((warpSize - __width) << 8) | (__Mask)); \
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} \
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inline __device__ unsigned int __FnName(unsigned int __val, __Type __offset, \
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int __width = warpSize) { \
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return static_cast<unsigned int>( \
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::__FnName(static_cast<int>(__val), __offset, __width)); \
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} \
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inline __device__ long long __FnName(long long __val, __Type __offset, \
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int __width = warpSize) { \
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struct __Bits { \
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int __a, __b; \
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}; \
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_Static_assert(sizeof(__val) == sizeof(__Bits)); \
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_Static_assert(sizeof(__Bits) == 2 * sizeof(int)); \
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__Bits __tmp; \
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memcpy(&__tmp, &__val, sizeof(__val)); \
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__tmp.__a = ::__FnName(__tmp.__a, __offset, __width); \
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__tmp.__b = ::__FnName(__tmp.__b, __offset, __width); \
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long long __ret; \
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memcpy(&__ret, &__tmp, sizeof(__tmp)); \
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return __ret; \
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} \
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inline __device__ long __FnName(long __val, __Type __offset, \
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int __width = warpSize) { \
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_Static_assert(sizeof(long) == sizeof(long long) || \
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sizeof(long) == sizeof(int)); \
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if (sizeof(long) == sizeof(long long)) { \
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return static_cast<long>( \
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::__FnName(static_cast<long long>(__val), __offset, __width)); \
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} else if (sizeof(long) == sizeof(int)) { \
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return static_cast<long>( \
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::__FnName(static_cast<int>(__val), __offset, __width)); \
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} \
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} \
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inline __device__ unsigned long __FnName( \
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unsigned long __val, __Type __offset, int __width = warpSize) { \
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return static_cast<unsigned long>( \
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::__FnName(static_cast<long>(__val), __offset, __width)); \
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} \
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inline __device__ unsigned long long __FnName( \
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unsigned long long __val, __Type __offset, int __width = warpSize) { \
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return static_cast<unsigned long long>( \
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::__FnName(static_cast<long long>(__val), __offset, __width)); \
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} \
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inline __device__ double __FnName(double __val, __Type __offset, \
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int __width = warpSize) { \
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long long __tmp; \
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_Static_assert(sizeof(__tmp) == sizeof(__val)); \
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memcpy(&__tmp, &__val, sizeof(__val)); \
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__tmp = ::__FnName(__tmp, __offset, __width); \
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double __ret; \
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memcpy(&__ret, &__tmp, sizeof(__ret)); \
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return __ret; \
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}
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__MAKE_SHUFFLES(__shfl, __nvvm_shfl_idx_i32, __nvvm_shfl_idx_f32, 0x1f, int);
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// We use 0 rather than 31 as our mask, because shfl.up applies to lanes >=
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// maxLane.
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__MAKE_SHUFFLES(__shfl_up, __nvvm_shfl_up_i32, __nvvm_shfl_up_f32, 0,
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unsigned int);
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__MAKE_SHUFFLES(__shfl_down, __nvvm_shfl_down_i32, __nvvm_shfl_down_f32, 0x1f,
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unsigned int);
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__MAKE_SHUFFLES(__shfl_xor, __nvvm_shfl_bfly_i32, __nvvm_shfl_bfly_f32, 0x1f,
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int);
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#pragma pop_macro("__MAKE_SHUFFLES")
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#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 300
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#if CUDA_VERSION >= 9000
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#if (!defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 300)
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// __shfl_sync_* variants available in CUDA-9
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#pragma push_macro("__MAKE_SYNC_SHUFFLES")
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#define __MAKE_SYNC_SHUFFLES(__FnName, __IntIntrinsic, __FloatIntrinsic, \
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__Mask, __Type) \
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inline __device__ int __FnName(unsigned int __mask, int __val, \
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__Type __offset, int __width = warpSize) { \
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return __IntIntrinsic(__mask, __val, __offset, \
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((warpSize - __width) << 8) | (__Mask)); \
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} \
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inline __device__ float __FnName(unsigned int __mask, float __val, \
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__Type __offset, int __width = warpSize) { \
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return __FloatIntrinsic(__mask, __val, __offset, \
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((warpSize - __width) << 8) | (__Mask)); \
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} \
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inline __device__ unsigned int __FnName(unsigned int __mask, \
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unsigned int __val, __Type __offset, \
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int __width = warpSize) { \
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return static_cast<unsigned int>( \
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::__FnName(__mask, static_cast<int>(__val), __offset, __width)); \
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} \
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inline __device__ long long __FnName(unsigned int __mask, long long __val, \
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__Type __offset, \
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int __width = warpSize) { \
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struct __Bits { \
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int __a, __b; \
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}; \
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_Static_assert(sizeof(__val) == sizeof(__Bits)); \
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_Static_assert(sizeof(__Bits) == 2 * sizeof(int)); \
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__Bits __tmp; \
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memcpy(&__tmp, &__val, sizeof(__val)); \
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__tmp.__a = ::__FnName(__mask, __tmp.__a, __offset, __width); \
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__tmp.__b = ::__FnName(__mask, __tmp.__b, __offset, __width); \
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long long __ret; \
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memcpy(&__ret, &__tmp, sizeof(__tmp)); \
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return __ret; \
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} \
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inline __device__ unsigned long long __FnName( \
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unsigned int __mask, unsigned long long __val, __Type __offset, \
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int __width = warpSize) { \
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return static_cast<unsigned long long>( \
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::__FnName(__mask, static_cast<long long>(__val), __offset, __width)); \
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} \
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inline __device__ long __FnName(unsigned int __mask, long __val, \
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__Type __offset, int __width = warpSize) { \
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_Static_assert(sizeof(long) == sizeof(long long) || \
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sizeof(long) == sizeof(int)); \
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if (sizeof(long) == sizeof(long long)) { \
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return static_cast<long>(::__FnName( \
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__mask, static_cast<long long>(__val), __offset, __width)); \
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} else if (sizeof(long) == sizeof(int)) { \
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return static_cast<long>( \
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::__FnName(__mask, static_cast<int>(__val), __offset, __width)); \
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} \
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} \
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inline __device__ unsigned long __FnName( \
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unsigned int __mask, unsigned long __val, __Type __offset, \
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int __width = warpSize) { \
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return static_cast<unsigned long>( \
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::__FnName(__mask, static_cast<long>(__val), __offset, __width)); \
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} \
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inline __device__ double __FnName(unsigned int __mask, double __val, \
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__Type __offset, int __width = warpSize) { \
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long long __tmp; \
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_Static_assert(sizeof(__tmp) == sizeof(__val)); \
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memcpy(&__tmp, &__val, sizeof(__val)); \
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__tmp = ::__FnName(__mask, __tmp, __offset, __width); \
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double __ret; \
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memcpy(&__ret, &__tmp, sizeof(__ret)); \
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return __ret; \
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}
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__MAKE_SYNC_SHUFFLES(__shfl_sync, __nvvm_shfl_sync_idx_i32,
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__nvvm_shfl_sync_idx_f32, 0x1f, int);
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// We use 0 rather than 31 as our mask, because shfl.up applies to lanes >=
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// maxLane.
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__MAKE_SYNC_SHUFFLES(__shfl_up_sync, __nvvm_shfl_sync_up_i32,
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__nvvm_shfl_sync_up_f32, 0, unsigned int);
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__MAKE_SYNC_SHUFFLES(__shfl_down_sync, __nvvm_shfl_sync_down_i32,
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__nvvm_shfl_sync_down_f32, 0x1f, unsigned int);
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__MAKE_SYNC_SHUFFLES(__shfl_xor_sync, __nvvm_shfl_sync_bfly_i32,
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__nvvm_shfl_sync_bfly_f32, 0x1f, int);
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#pragma pop_macro("__MAKE_SYNC_SHUFFLES")
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inline __device__ void __syncwarp(unsigned int mask = 0xffffffff) {
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return __nvvm_bar_warp_sync(mask);
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}
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inline __device__ void __barrier_sync(unsigned int id) {
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__nvvm_barrier_sync(id);
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}
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inline __device__ void __barrier_sync_count(unsigned int id,
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unsigned int count) {
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__nvvm_barrier_sync_cnt(id, count);
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}
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inline __device__ int __all_sync(unsigned int mask, int pred) {
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return __nvvm_vote_all_sync(mask, pred);
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}
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inline __device__ int __any_sync(unsigned int mask, int pred) {
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return __nvvm_vote_any_sync(mask, pred);
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}
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inline __device__ int __uni_sync(unsigned int mask, int pred) {
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return __nvvm_vote_uni_sync(mask, pred);
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}
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inline __device__ unsigned int __ballot_sync(unsigned int mask, int pred) {
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return __nvvm_vote_ballot_sync(mask, pred);
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}
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inline __device__ unsigned int __activemask() {
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#if CUDA_VERSION < 9020
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return __nvvm_vote_ballot(1);
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#else
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return __nvvm_activemask();
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#endif
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}
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inline __device__ unsigned int __fns(unsigned mask, unsigned base, int offset) {
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return __nvvm_fns(mask, base, offset);
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}
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#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 300
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// Define __match* builtins CUDA-9 headers expect to see.
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#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 700
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inline __device__ unsigned int __match32_any_sync(unsigned int mask,
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unsigned int value) {
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return __nvvm_match_any_sync_i32(mask, value);
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}
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inline __device__ unsigned int
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__match64_any_sync(unsigned int mask, unsigned long long value) {
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return __nvvm_match_any_sync_i64(mask, value);
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}
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inline __device__ unsigned int
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__match32_all_sync(unsigned int mask, unsigned int value, int *pred) {
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return __nvvm_match_all_sync_i32p(mask, value, pred);
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}
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inline __device__ unsigned int
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__match64_all_sync(unsigned int mask, unsigned long long value, int *pred) {
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return __nvvm_match_all_sync_i64p(mask, value, pred);
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}
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#include "crt/sm_70_rt.hpp"
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#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 700
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#endif // __CUDA_VERSION >= 9000
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// sm_32 intrinsics: __ldg and __funnelshift_{l,lc,r,rc}.
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// Prevent the vanilla sm_32 intrinsics header from being included.
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#define __SM_32_INTRINSICS_H__
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#define __SM_32_INTRINSICS_HPP__
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#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 320
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inline __device__ char __ldg(const char *ptr) { return __nvvm_ldg_c(ptr); }
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inline __device__ short __ldg(const short *ptr) { return __nvvm_ldg_s(ptr); }
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inline __device__ int __ldg(const int *ptr) { return __nvvm_ldg_i(ptr); }
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inline __device__ long __ldg(const long *ptr) { return __nvvm_ldg_l(ptr); }
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inline __device__ long long __ldg(const long long *ptr) {
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return __nvvm_ldg_ll(ptr);
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}
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inline __device__ unsigned char __ldg(const unsigned char *ptr) {
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return __nvvm_ldg_uc(ptr);
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}
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inline __device__ signed char __ldg(const signed char *ptr) {
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return __nvvm_ldg_uc((const unsigned char *)ptr);
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}
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inline __device__ unsigned short __ldg(const unsigned short *ptr) {
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return __nvvm_ldg_us(ptr);
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}
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inline __device__ unsigned int __ldg(const unsigned int *ptr) {
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return __nvvm_ldg_ui(ptr);
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}
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inline __device__ unsigned long __ldg(const unsigned long *ptr) {
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return __nvvm_ldg_ul(ptr);
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}
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inline __device__ unsigned long long __ldg(const unsigned long long *ptr) {
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return __nvvm_ldg_ull(ptr);
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}
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inline __device__ float __ldg(const float *ptr) { return __nvvm_ldg_f(ptr); }
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inline __device__ double __ldg(const double *ptr) { return __nvvm_ldg_d(ptr); }
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inline __device__ char2 __ldg(const char2 *ptr) {
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typedef char c2 __attribute__((ext_vector_type(2)));
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// We can assume that ptr is aligned at least to char2's alignment, but the
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// load will assume that ptr is aligned to char2's alignment. This is only
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// safe if alignof(c2) <= alignof(char2).
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c2 rv = __nvvm_ldg_c2(reinterpret_cast<const c2 *>(ptr));
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char2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ char4 __ldg(const char4 *ptr) {
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typedef char c4 __attribute__((ext_vector_type(4)));
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c4 rv = __nvvm_ldg_c4(reinterpret_cast<const c4 *>(ptr));
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char4 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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ret.z = rv[2];
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ret.w = rv[3];
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return ret;
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}
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inline __device__ short2 __ldg(const short2 *ptr) {
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typedef short s2 __attribute__((ext_vector_type(2)));
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s2 rv = __nvvm_ldg_s2(reinterpret_cast<const s2 *>(ptr));
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short2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ short4 __ldg(const short4 *ptr) {
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typedef short s4 __attribute__((ext_vector_type(4)));
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s4 rv = __nvvm_ldg_s4(reinterpret_cast<const s4 *>(ptr));
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short4 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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ret.z = rv[2];
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ret.w = rv[3];
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return ret;
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}
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inline __device__ int2 __ldg(const int2 *ptr) {
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typedef int i2 __attribute__((ext_vector_type(2)));
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i2 rv = __nvvm_ldg_i2(reinterpret_cast<const i2 *>(ptr));
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int2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ int4 __ldg(const int4 *ptr) {
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typedef int i4 __attribute__((ext_vector_type(4)));
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i4 rv = __nvvm_ldg_i4(reinterpret_cast<const i4 *>(ptr));
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int4 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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ret.z = rv[2];
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ret.w = rv[3];
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return ret;
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}
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inline __device__ longlong2 __ldg(const longlong2 *ptr) {
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typedef long long ll2 __attribute__((ext_vector_type(2)));
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ll2 rv = __nvvm_ldg_ll2(reinterpret_cast<const ll2 *>(ptr));
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longlong2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ uchar2 __ldg(const uchar2 *ptr) {
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typedef unsigned char uc2 __attribute__((ext_vector_type(2)));
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uc2 rv = __nvvm_ldg_uc2(reinterpret_cast<const uc2 *>(ptr));
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uchar2 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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return ret;
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}
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inline __device__ uchar4 __ldg(const uchar4 *ptr) {
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typedef unsigned char uc4 __attribute__((ext_vector_type(4)));
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uc4 rv = __nvvm_ldg_uc4(reinterpret_cast<const uc4 *>(ptr));
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uchar4 ret;
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ret.x = rv[0];
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ret.y = rv[1];
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ret.z = rv[2];
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ret.w = rv[3];
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return ret;
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}
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inline __device__ ushort2 __ldg(const ushort2 *ptr) {
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typedef unsigned short us2 __attribute__((ext_vector_type(2)));
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us2 rv = __nvvm_ldg_us2(reinterpret_cast<const us2 *>(ptr));
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ushort2 ret;
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ret.x = rv[0];
|
|
ret.y = rv[1];
|
|
return ret;
|
|
}
|
|
inline __device__ ushort4 __ldg(const ushort4 *ptr) {
|
|
typedef unsigned short us4 __attribute__((ext_vector_type(4)));
|
|
us4 rv = __nvvm_ldg_us4(reinterpret_cast<const us4 *>(ptr));
|
|
ushort4 ret;
|
|
ret.x = rv[0];
|
|
ret.y = rv[1];
|
|
ret.z = rv[2];
|
|
ret.w = rv[3];
|
|
return ret;
|
|
}
|
|
inline __device__ uint2 __ldg(const uint2 *ptr) {
|
|
typedef unsigned int ui2 __attribute__((ext_vector_type(2)));
|
|
ui2 rv = __nvvm_ldg_ui2(reinterpret_cast<const ui2 *>(ptr));
|
|
uint2 ret;
|
|
ret.x = rv[0];
|
|
ret.y = rv[1];
|
|
return ret;
|
|
}
|
|
inline __device__ uint4 __ldg(const uint4 *ptr) {
|
|
typedef unsigned int ui4 __attribute__((ext_vector_type(4)));
|
|
ui4 rv = __nvvm_ldg_ui4(reinterpret_cast<const ui4 *>(ptr));
|
|
uint4 ret;
|
|
ret.x = rv[0];
|
|
ret.y = rv[1];
|
|
ret.z = rv[2];
|
|
ret.w = rv[3];
|
|
return ret;
|
|
}
|
|
inline __device__ ulonglong2 __ldg(const ulonglong2 *ptr) {
|
|
typedef unsigned long long ull2 __attribute__((ext_vector_type(2)));
|
|
ull2 rv = __nvvm_ldg_ull2(reinterpret_cast<const ull2 *>(ptr));
|
|
ulonglong2 ret;
|
|
ret.x = rv[0];
|
|
ret.y = rv[1];
|
|
return ret;
|
|
}
|
|
|
|
inline __device__ float2 __ldg(const float2 *ptr) {
|
|
typedef float f2 __attribute__((ext_vector_type(2)));
|
|
f2 rv = __nvvm_ldg_f2(reinterpret_cast<const f2 *>(ptr));
|
|
float2 ret;
|
|
ret.x = rv[0];
|
|
ret.y = rv[1];
|
|
return ret;
|
|
}
|
|
inline __device__ float4 __ldg(const float4 *ptr) {
|
|
typedef float f4 __attribute__((ext_vector_type(4)));
|
|
f4 rv = __nvvm_ldg_f4(reinterpret_cast<const f4 *>(ptr));
|
|
float4 ret;
|
|
ret.x = rv[0];
|
|
ret.y = rv[1];
|
|
ret.z = rv[2];
|
|
ret.w = rv[3];
|
|
return ret;
|
|
}
|
|
inline __device__ double2 __ldg(const double2 *ptr) {
|
|
typedef double d2 __attribute__((ext_vector_type(2)));
|
|
d2 rv = __nvvm_ldg_d2(reinterpret_cast<const d2 *>(ptr));
|
|
double2 ret;
|
|
ret.x = rv[0];
|
|
ret.y = rv[1];
|
|
return ret;
|
|
}
|
|
|
|
// TODO: Implement these as intrinsics, so the backend can work its magic on
|
|
// these. Alternatively, we could implement these as plain C and try to get
|
|
// llvm to recognize the relevant patterns.
|
|
inline __device__ unsigned __funnelshift_l(unsigned low32, unsigned high32,
|
|
unsigned shiftWidth) {
|
|
unsigned result;
|
|
__asm__("shf.l.wrap.b32 %0, %1, %2, %3;"
|
|
: "=r"(result)
|
|
: "r"(low32), "r"(high32), "r"(shiftWidth));
|
|
return result;
|
|
}
|
|
inline __device__ unsigned __funnelshift_lc(unsigned low32, unsigned high32,
|
|
unsigned shiftWidth) {
|
|
unsigned result;
|
|
__asm__("shf.l.clamp.b32 %0, %1, %2, %3;"
|
|
: "=r"(result)
|
|
: "r"(low32), "r"(high32), "r"(shiftWidth));
|
|
return result;
|
|
}
|
|
inline __device__ unsigned __funnelshift_r(unsigned low32, unsigned high32,
|
|
unsigned shiftWidth) {
|
|
unsigned result;
|
|
__asm__("shf.r.wrap.b32 %0, %1, %2, %3;"
|
|
: "=r"(result)
|
|
: "r"(low32), "r"(high32), "r"(shiftWidth));
|
|
return result;
|
|
}
|
|
inline __device__ unsigned __funnelshift_rc(unsigned low32, unsigned high32,
|
|
unsigned shiftWidth) {
|
|
unsigned ret;
|
|
__asm__("shf.r.clamp.b32 %0, %1, %2, %3;"
|
|
: "=r"(ret)
|
|
: "r"(low32), "r"(high32), "r"(shiftWidth));
|
|
return ret;
|
|
}
|
|
|
|
#if defined(__cplusplus) && (__cplusplus >= 201103L)
|
|
|
|
#pragma push_macro("__INTRINSIC_LOAD")
|
|
#define __INTRINSIC_LOAD(__FnName, __AsmOp, __DeclType, __TmpType, __AsmType, \
|
|
__Volatile, __Clobber) \
|
|
inline __device__ __DeclType __FnName(const __DeclType *__ptr) { \
|
|
__TmpType __ret; \
|
|
__asm__ __Volatile(__AsmOp " %0, [%1];" \
|
|
: __AsmType(__ret) \
|
|
: "l"(__ptr)__Clobber); \
|
|
return (__DeclType)__ret; \
|
|
}
|
|
|
|
#pragma push_macro("__INTRINSIC_LOAD2")
|
|
#define __INTRINSIC_LOAD2(__FnName, __AsmOp, __DeclType, __TmpType, __AsmType, \
|
|
__Volatile, __Clobber) \
|
|
inline __device__ __DeclType __FnName(const __DeclType *__ptr) { \
|
|
__DeclType __ret; \
|
|
__TmpType __tmp; \
|
|
__asm__ __Volatile(__AsmOp " {%0,%1}, [%2];" \
|
|
: __AsmType(__tmp.x), __AsmType(__tmp.y) \
|
|
: "l"(__ptr)__Clobber); \
|
|
using __ElementType = decltype(__ret.x); \
|
|
__ret.x = (__ElementType)__tmp.x; \
|
|
__ret.y = (__ElementType)__tmp.y; \
|
|
return __ret; \
|
|
}
|
|
|
|
#pragma push_macro("__INTRINSIC_LOAD4")
|
|
#define __INTRINSIC_LOAD4(__FnName, __AsmOp, __DeclType, __TmpType, __AsmType, \
|
|
__Volatile, __Clobber) \
|
|
inline __device__ __DeclType __FnName(const __DeclType *__ptr) { \
|
|
__DeclType __ret; \
|
|
__TmpType __tmp; \
|
|
__asm__ __Volatile(__AsmOp " {%0,%1,%2,%3}, [%4];" \
|
|
: __AsmType(__tmp.x), __AsmType(__tmp.y), \
|
|
__AsmType(__tmp.z), __AsmType(__tmp.w) \
|
|
: "l"(__ptr)__Clobber); \
|
|
using __ElementType = decltype(__ret.x); \
|
|
__ret.x = (__ElementType)__tmp.x; \
|
|
__ret.y = (__ElementType)__tmp.y; \
|
|
__ret.z = (__ElementType)__tmp.z; \
|
|
__ret.w = (__ElementType)__tmp.w; \
|
|
return __ret; \
|
|
}
|
|
|
|
#pragma push_macro("__INTRINSIC_LOAD_LONG")
|
|
#define __INTRINSIC_LOAD_LONG(__Mode) \
|
|
inline __device__ long __ld##__Mode(const long *__ptr) { \
|
|
if (__SIZEOF_LONG__ == __SIZEOF_LONG_LONG__) { \
|
|
return (long)__ld##__Mode((const long long *)__ptr); \
|
|
} else { \
|
|
return (long)__ld##__Mode((const int *)__ptr); \
|
|
} \
|
|
}
|
|
|
|
#pragma push_macro("__INTRINSIC_LOAD_ULONG")
|
|
#define __INTRINSIC_LOAD_ULONG(__Mode) \
|
|
inline __device__ unsigned long __ld##__Mode(const unsigned long *__ptr) { \
|
|
if (__SIZEOF_LONG__ == __SIZEOF_LONG_LONG__) { \
|
|
return (unsigned long)__ld##__Mode((const unsigned long long *)__ptr); \
|
|
} else { \
|
|
return (unsigned long)__ld##__Mode((const unsigned int *)__ptr); \
|
|
} \
|
|
}
|
|
|
|
#define __INTRINSIC_LOAD_FAMILY(__Mode, __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".s8", char, \
|
|
unsigned int, "=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".s8", signed char, \
|
|
unsigned int, "=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".s16", short, \
|
|
unsigned short, "=h", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".s32", int, \
|
|
unsigned int, "=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".s64", long long, \
|
|
unsigned long long, "=l", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD2(__ld##__Mode, "ld.global." #__Mode ".v2.s8", char2, int2, \
|
|
"=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD4(__ld##__Mode, "ld.global." #__Mode ".v4.s8", char4, int4, \
|
|
"=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD2(__ld##__Mode, "ld.global." #__Mode ".v2.s16", short2, \
|
|
short2, "=h", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD4(__ld##__Mode, "ld.global." #__Mode ".v4.s16", short4, \
|
|
short4, "=h", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD2(__ld##__Mode, "ld.global." #__Mode ".v2.s32", int2, int2, \
|
|
"=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD4(__ld##__Mode, "ld.global." #__Mode ".v4.s32", int4, int4, \
|
|
"=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD2(__ld##__Mode, "ld.global." #__Mode ".v2.s64", longlong2, \
|
|
longlong2, "=l", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".u8", unsigned char, \
|
|
unsigned int, "=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".u16", unsigned short, \
|
|
unsigned short, "=h", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".u32", unsigned int, \
|
|
unsigned int, "=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".u64", \
|
|
unsigned long long, unsigned long long, "=l", __Volatile, \
|
|
__Clobber) \
|
|
__INTRINSIC_LOAD2(__ld##__Mode, "ld.global." #__Mode ".v2.u8", uchar2, \
|
|
uint2, "=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD4(__ld##__Mode, "ld.global." #__Mode ".v4.u8", uchar4, \
|
|
uint4, "=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD2(__ld##__Mode, "ld.global." #__Mode ".v2.u16", ushort2, \
|
|
ushort2, "=h", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD4(__ld##__Mode, "ld.global." #__Mode ".v4.u16", ushort4, \
|
|
ushort4, "=h", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD2(__ld##__Mode, "ld.global." #__Mode ".v2.u32", uint2, \
|
|
uint2, "=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD4(__ld##__Mode, "ld.global." #__Mode ".v4.u32", uint4, \
|
|
uint4, "=r", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD2(__ld##__Mode, "ld.global." #__Mode ".v2.u64", ulonglong2, \
|
|
ulonglong2, "=l", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".f32", float, float, \
|
|
"=f", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD(__ld##__Mode, "ld.global." #__Mode ".f64", double, double, \
|
|
"=d", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD2(__ld##__Mode, "ld.global." #__Mode ".v2.f32", float2, \
|
|
float2, "=f", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD4(__ld##__Mode, "ld.global." #__Mode ".v4.f32", float4, \
|
|
float4, "=f", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD2(__ld##__Mode, "ld.global." #__Mode ".v2.f64", double2, \
|
|
double2, "=d", __Volatile, __Clobber) \
|
|
__INTRINSIC_LOAD_LONG(__Mode) \
|
|
__INTRINSIC_LOAD_ULONG(__Mode)
|
|
|
|
__INTRINSIC_LOAD_FAMILY(ca, __volatile__, /* no clobber */)
|
|
__INTRINSIC_LOAD_FAMILY(cg, __volatile__, /* no clobber */)
|
|
__INTRINSIC_LOAD_FAMILY(cs, __volatile__, /* no clobber */)
|
|
__INTRINSIC_LOAD_FAMILY(cv, /* not volatile */, : "memory")
|
|
__INTRINSIC_LOAD_FAMILY(lu, /* not volatile */, : "memory")
|
|
|
|
#pragma pop_macro("__INTRINSIC_LOAD")
|
|
#pragma pop_macro("__INTRINSIC_LOAD2")
|
|
#pragma pop_macro("__INTRINSIC_LOAD4")
|
|
#pragma pop_macro("__INTRINSIC_LOAD_LONG")
|
|
#pragma pop_macro("__INTRINSIC_LOAD_ULONG")
|
|
#pragma pop_macro("__INTRINSIC_LOAD_FAMILY")
|
|
|
|
#pragma push_macro("__INTRINSIC_STORE")
|
|
#define __INTRINSIC_STORE(__FnName, __AsmOp, __DeclType, __TmpType, __AsmType) \
|
|
inline __device__ void __FnName(__DeclType *__ptr, __DeclType __value) { \
|
|
__TmpType __tmp = (__TmpType)__value; \
|
|
__asm__(__AsmOp " [%0], %1;" ::"l"(__ptr), __AsmType(__tmp) : "memory"); \
|
|
}
|
|
|
|
#pragma push_macro("__INTRINSIC_STORE2")
|
|
#define __INTRINSIC_STORE2(__FnName, __AsmOp, __DeclType, __TmpType, \
|
|
__AsmType) \
|
|
inline __device__ void __FnName(__DeclType *__ptr, __DeclType __value) { \
|
|
__TmpType __tmp; \
|
|
using __ElementType = decltype(__tmp.x); \
|
|
__tmp.x = (__ElementType)(__value.x); \
|
|
__tmp.y = (__ElementType)(__value.y); \
|
|
__asm__(__AsmOp " [%0], {%1,%2};" ::"l"(__ptr), __AsmType(__tmp.x), \
|
|
__AsmType(__tmp.y) \
|
|
: "memory"); \
|
|
}
|
|
|
|
#pragma push_macro("__INTRINSIC_STORE4")
|
|
#define __INTRINSIC_STORE4(__FnName, __AsmOp, __DeclType, __TmpType, \
|
|
__AsmType) \
|
|
inline __device__ void __FnName(__DeclType *__ptr, __DeclType __value) { \
|
|
__TmpType __tmp; \
|
|
using __ElementType = decltype(__tmp.x); \
|
|
__tmp.x = (__ElementType)(__value.x); \
|
|
__tmp.y = (__ElementType)(__value.y); \
|
|
__tmp.z = (__ElementType)(__value.z); \
|
|
__tmp.w = (__ElementType)(__value.w); \
|
|
__asm__(__AsmOp " [%0], {%1,%2,%3,%4};" ::"l"(__ptr), __AsmType(__tmp.x), \
|
|
__AsmType(__tmp.y), __AsmType(__tmp.z), __AsmType(__tmp.w) \
|
|
: "memory"); \
|
|
}
|
|
|
|
#pragma push_macro("__INTRINSIC_STORE_LONG")
|
|
#define __INTRINSIC_STORE_LONG(__Mode) \
|
|
inline __device__ void __st##__Mode(long *__ptr, long __value) { \
|
|
if (__SIZEOF_LONG__ == __SIZEOF_LONG_LONG__) { \
|
|
__st##__Mode((long long *)__ptr, (long long)__value); \
|
|
} else { \
|
|
__st##__Mode((int *)__ptr, (int)__value); \
|
|
} \
|
|
}
|
|
|
|
#pragma push_macro("__INTRINSIC_STORE_ULONG")
|
|
#define __INTRINSIC_STORE_ULONG(__Mode) \
|
|
inline __device__ void __st##__Mode(unsigned long *__ptr, \
|
|
unsigned long __value) { \
|
|
if (__SIZEOF_LONG__ == __SIZEOF_LONG_LONG__) { \
|
|
__st##__Mode((unsigned long long *)__ptr, (unsigned long long)__value); \
|
|
} else { \
|
|
__st##__Mode((unsigned int *)__ptr, (unsigned int)__value); \
|
|
} \
|
|
}
|
|
|
|
#pragma push_macro("__INTRINSIC_STORE_FAMILY")
|
|
#define __INTRINSIC_STORE_FAMILY(__Mode) \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".s8", char, int, "r") \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".s8", signed char, \
|
|
int, "r") \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".s16", short, short, \
|
|
"h") \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".s32", int, int, "r") \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".s64", long long, \
|
|
long long, "l") \
|
|
__INTRINSIC_STORE2(__st##__Mode, "st.global." #__Mode ".v2.s8", char2, int2, \
|
|
"r") \
|
|
__INTRINSIC_STORE4(__st##__Mode, "st.global." #__Mode ".v4.s8", char4, int4, \
|
|
"r") \
|
|
__INTRINSIC_STORE2(__st##__Mode, "st.global." #__Mode ".v2.s16", short2, \
|
|
short2, "h") \
|
|
__INTRINSIC_STORE4(__st##__Mode, "st.global." #__Mode ".v4.s16", short4, \
|
|
short4, "h") \
|
|
__INTRINSIC_STORE2(__st##__Mode, "st.global." #__Mode ".v2.s32", int2, int2, \
|
|
"r") \
|
|
__INTRINSIC_STORE4(__st##__Mode, "st.global." #__Mode ".v4.s32", int4, int4, \
|
|
"r") \
|
|
__INTRINSIC_STORE2(__st##__Mode, "st.global." #__Mode ".v2.s64", longlong2, \
|
|
longlong2, "l") \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".u8", unsigned char, \
|
|
int, "r") \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".u16", unsigned short, \
|
|
unsigned short, "h") \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".u32", unsigned int, \
|
|
unsigned int, "r") \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".u64", \
|
|
unsigned long long, unsigned long long, "l") \
|
|
__INTRINSIC_STORE2(__st##__Mode, "st.global." #__Mode ".v2.u8", uchar2, \
|
|
uchar2, "r") \
|
|
__INTRINSIC_STORE4(__st##__Mode, "st.global." #__Mode ".v4.u8", uchar4, \
|
|
uint4, "r") \
|
|
__INTRINSIC_STORE2(__st##__Mode, "st.global." #__Mode ".v2.u16", ushort2, \
|
|
ushort2, "h") \
|
|
__INTRINSIC_STORE4(__st##__Mode, "st.global." #__Mode ".v4.u16", ushort4, \
|
|
ushort4, "h") \
|
|
__INTRINSIC_STORE2(__st##__Mode, "st.global." #__Mode ".v2.u32", uint2, \
|
|
uint2, "r") \
|
|
__INTRINSIC_STORE4(__st##__Mode, "st.global." #__Mode ".v4.u32", uint4, \
|
|
uint4, "r") \
|
|
__INTRINSIC_STORE2(__st##__Mode, "st.global." #__Mode ".v2.u64", ulonglong2, \
|
|
ulonglong2, "l") \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".f32", float, float, \
|
|
"f") \
|
|
__INTRINSIC_STORE(__st##__Mode, "st.global." #__Mode ".f64", double, double, \
|
|
"d") \
|
|
__INTRINSIC_STORE2(__st##__Mode, "st.global." #__Mode ".v2.f32", float2, \
|
|
float2, "f") \
|
|
__INTRINSIC_STORE4(__st##__Mode, "st.global." #__Mode ".v4.f32", float4, \
|
|
float4, "f") \
|
|
__INTRINSIC_STORE2(__st##__Mode, "st.global." #__Mode ".v2.f64", double2, \
|
|
double2, "d") \
|
|
__INTRINSIC_STORE_LONG(__Mode) \
|
|
__INTRINSIC_STORE_ULONG(__Mode)
|
|
|
|
__INTRINSIC_STORE_FAMILY(cg)
|
|
__INTRINSIC_STORE_FAMILY(cs)
|
|
__INTRINSIC_STORE_FAMILY(wb)
|
|
__INTRINSIC_STORE_FAMILY(wt)
|
|
|
|
#pragma pop_macro("__INTRINSIC_STORE")
|
|
#pragma pop_macro("__INTRINSIC_STORE2")
|
|
#pragma pop_macro("__INTRINSIC_STORE4")
|
|
#pragma pop_macro("__INTRINSIC_STORE_LONG")
|
|
#pragma pop_macro("__INTRINSIC_STORE_ULONG")
|
|
#pragma pop_macro("__INTRINSIC_STORE_FAMILY")
|
|
|
|
#endif // defined(__cplusplus) && (__cplusplus >= 201103L)
|
|
#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 320
|
|
|
|
#if CUDA_VERSION >= 11000
|
|
extern "C" {
|
|
__device__ inline size_t __nv_cvta_generic_to_global_impl(const void *__ptr) {
|
|
return (size_t)(void __attribute__((address_space(1))) *)__ptr;
|
|
}
|
|
__device__ inline size_t __nv_cvta_generic_to_shared_impl(const void *__ptr) {
|
|
return (size_t)(void __attribute__((address_space(3))) *)__ptr;
|
|
}
|
|
__device__ inline size_t __nv_cvta_generic_to_constant_impl(const void *__ptr) {
|
|
return (size_t)(void __attribute__((address_space(4))) *)__ptr;
|
|
}
|
|
__device__ inline size_t __nv_cvta_generic_to_local_impl(const void *__ptr) {
|
|
return (size_t)(void __attribute__((address_space(5))) *)__ptr;
|
|
}
|
|
__device__ inline void *__nv_cvta_global_to_generic_impl(size_t __ptr) {
|
|
return (void *)(void __attribute__((address_space(1))) *)__ptr;
|
|
}
|
|
__device__ inline void *__nv_cvta_shared_to_generic_impl(size_t __ptr) {
|
|
return (void *)(void __attribute__((address_space(3))) *)__ptr;
|
|
}
|
|
__device__ inline void *__nv_cvta_constant_to_generic_impl(size_t __ptr) {
|
|
return (void *)(void __attribute__((address_space(4))) *)__ptr;
|
|
}
|
|
__device__ inline void *__nv_cvta_local_to_generic_impl(size_t __ptr) {
|
|
return (void *)(void __attribute__((address_space(5))) *)__ptr;
|
|
}
|
|
__device__ inline cuuint32_t __nvvm_get_smem_pointer(void *__ptr) {
|
|
return __nv_cvta_generic_to_shared_impl(__ptr);
|
|
}
|
|
} // extern "C"
|
|
|
|
#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 800
|
|
__device__ inline unsigned __reduce_add_sync(unsigned __mask,
|
|
unsigned __value) {
|
|
return __nvvm_redux_sync_add(__value, __mask);
|
|
}
|
|
__device__ inline unsigned __reduce_min_sync(unsigned __mask,
|
|
unsigned __value) {
|
|
return __nvvm_redux_sync_umin(__value, __mask);
|
|
}
|
|
__device__ inline unsigned __reduce_max_sync(unsigned __mask,
|
|
unsigned __value) {
|
|
return __nvvm_redux_sync_umax(__value, __mask);
|
|
}
|
|
__device__ inline int __reduce_min_sync(unsigned __mask, int __value) {
|
|
return __nvvm_redux_sync_min(__value, __mask);
|
|
}
|
|
__device__ inline int __reduce_max_sync(unsigned __mask, int __value) {
|
|
return __nvvm_redux_sync_max(__value, __mask);
|
|
}
|
|
__device__ inline unsigned __reduce_or_sync(unsigned __mask, unsigned __value) {
|
|
return __nvvm_redux_sync_or(__value, __mask);
|
|
}
|
|
__device__ inline unsigned __reduce_and_sync(unsigned __mask,
|
|
unsigned __value) {
|
|
return __nvvm_redux_sync_and(__value, __mask);
|
|
}
|
|
__device__ inline unsigned __reduce_xor_sync(unsigned __mask,
|
|
unsigned __value) {
|
|
return __nvvm_redux_sync_xor(__value, __mask);
|
|
}
|
|
|
|
__device__ inline void __nv_memcpy_async_shared_global_4(void *__dst,
|
|
const void *__src,
|
|
unsigned __src_size) {
|
|
__nvvm_cp_async_ca_shared_global_4(
|
|
(void __attribute__((address_space(3))) *)__dst,
|
|
(const void __attribute__((address_space(1))) *)__src, __src_size);
|
|
}
|
|
__device__ inline void __nv_memcpy_async_shared_global_8(void *__dst,
|
|
const void *__src,
|
|
unsigned __src_size) {
|
|
__nvvm_cp_async_ca_shared_global_8(
|
|
(void __attribute__((address_space(3))) *)__dst,
|
|
(const void __attribute__((address_space(1))) *)__src, __src_size);
|
|
}
|
|
__device__ inline void __nv_memcpy_async_shared_global_16(void *__dst,
|
|
const void *__src,
|
|
unsigned __src_size) {
|
|
__nvvm_cp_async_ca_shared_global_16(
|
|
(void __attribute__((address_space(3))) *)__dst,
|
|
(const void __attribute__((address_space(1))) *)__src, __src_size);
|
|
}
|
|
|
|
__device__ inline void *
|
|
__nv_associate_access_property(const void *__ptr, unsigned long long __prop) {
|
|
// TODO: it appears to provide compiler with some sort of a hint. We do not
|
|
// know what exactly it is supposed to do. However, CUDA headers suggest that
|
|
// just passing through __ptr should not affect correctness. They do so on
|
|
// pre-sm80 GPUs where this builtin is not available.
|
|
return (void*)__ptr;
|
|
}
|
|
#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 800
|
|
|
|
#if !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 900
|
|
__device__ inline unsigned __isCtaShared(const void *ptr) {
|
|
return __isShared(ptr);
|
|
}
|
|
|
|
__device__ inline unsigned __isClusterShared(const void *__ptr) {
|
|
return __nvvm_isspacep_shared_cluster(__ptr);
|
|
}
|
|
|
|
__device__ inline void *__cluster_map_shared_rank(const void *__ptr,
|
|
unsigned __rank) {
|
|
return __nvvm_mapa((void *)__ptr, __rank);
|
|
}
|
|
|
|
__device__ inline unsigned __cluster_query_shared_rank(const void *__ptr) {
|
|
return __nvvm_getctarank((void *)__ptr);
|
|
}
|
|
|
|
__device__ inline uint2
|
|
__cluster_map_shared_multicast(const void *__ptr,
|
|
unsigned int __cluster_cta_mask) {
|
|
return make_uint2((unsigned)__cvta_generic_to_shared(__ptr),
|
|
__cluster_cta_mask);
|
|
}
|
|
|
|
__device__ inline unsigned __clusterDimIsSpecified() {
|
|
return __nvvm_is_explicit_cluster();
|
|
}
|
|
|
|
__device__ inline dim3 __clusterDim() {
|
|
return dim3(__nvvm_read_ptx_sreg_cluster_nctaid_x(),
|
|
__nvvm_read_ptx_sreg_cluster_nctaid_y(),
|
|
__nvvm_read_ptx_sreg_cluster_nctaid_z());
|
|
}
|
|
|
|
__device__ inline dim3 __clusterRelativeBlockIdx() {
|
|
return dim3(__nvvm_read_ptx_sreg_cluster_ctaid_x(),
|
|
__nvvm_read_ptx_sreg_cluster_ctaid_y(),
|
|
__nvvm_read_ptx_sreg_cluster_ctaid_z());
|
|
}
|
|
|
|
__device__ inline dim3 __clusterGridDimInClusters() {
|
|
return dim3(__nvvm_read_ptx_sreg_nclusterid_x(),
|
|
__nvvm_read_ptx_sreg_nclusterid_y(),
|
|
__nvvm_read_ptx_sreg_nclusterid_z());
|
|
}
|
|
|
|
__device__ inline dim3 __clusterIdx() {
|
|
return dim3(__nvvm_read_ptx_sreg_clusterid_x(),
|
|
__nvvm_read_ptx_sreg_clusterid_y(),
|
|
__nvvm_read_ptx_sreg_clusterid_z());
|
|
}
|
|
|
|
__device__ inline unsigned __clusterRelativeBlockRank() {
|
|
return __nvvm_read_ptx_sreg_cluster_ctarank();
|
|
}
|
|
|
|
__device__ inline unsigned __clusterSizeInBlocks() {
|
|
return __nvvm_read_ptx_sreg_cluster_nctarank();
|
|
}
|
|
|
|
__device__ inline void __cluster_barrier_arrive() {
|
|
__nvvm_barrier_cluster_arrive();
|
|
}
|
|
|
|
__device__ inline void __cluster_barrier_arrive_relaxed() {
|
|
__nvvm_barrier_cluster_arrive_relaxed();
|
|
}
|
|
|
|
__device__ inline void __cluster_barrier_wait() {
|
|
__nvvm_barrier_cluster_wait();
|
|
}
|
|
|
|
__device__ inline void __threadfence_cluster() { __nvvm_fence_sc_cluster(); }
|
|
|
|
__device__ inline float2 atomicAdd(float2 *__ptr, float2 __val) {
|
|
float2 __ret;
|
|
__asm__("atom.add.v2.f32 {%0, %1}, [%2], {%3, %4};"
|
|
: "=f"(__ret.x), "=f"(__ret.y)
|
|
: "l"(__ptr), "f"(__val.x), "f"(__val.y));
|
|
return __ret;
|
|
}
|
|
|
|
__device__ inline float2 atomicAdd_block(float2 *__ptr, float2 __val) {
|
|
float2 __ret;
|
|
__asm__("atom.cta.add.v2.f32 {%0, %1}, [%2], {%3, %4};"
|
|
: "=f"(__ret.x), "=f"(__ret.y)
|
|
: "l"(__ptr), "f"(__val.x), "f"(__val.y));
|
|
return __ret;
|
|
}
|
|
|
|
__device__ inline float2 atomicAdd_system(float2 *__ptr, float2 __val) {
|
|
float2 __ret;
|
|
__asm__("atom.sys.add.v2.f32 {%0, %1}, [%2], {%3, %4};"
|
|
: "=f"(__ret.x), "=f"(__ret.y)
|
|
: "l"(__ptr), "f"(__val.x), "f"(__val.y));
|
|
return __ret;
|
|
}
|
|
|
|
__device__ inline float4 atomicAdd(float4 *__ptr, float4 __val) {
|
|
float4 __ret;
|
|
__asm__("atom.add.v4.f32 {%0, %1, %2, %3}, [%4], {%5, %6, %7, %8};"
|
|
: "=f"(__ret.x), "=f"(__ret.y), "=f"(__ret.z), "=f"(__ret.w)
|
|
: "l"(__ptr), "f"(__val.x), "f"(__val.y), "f"(__val.z), "f"(__val.w));
|
|
return __ret;
|
|
}
|
|
|
|
__device__ inline float4 atomicAdd_block(float4 *__ptr, float4 __val) {
|
|
float4 __ret;
|
|
__asm__(
|
|
"atom.cta.add.v4.f32 {%0, %1, %2, %3}, [%4], {%5, %6, %7, %8};"
|
|
: "=f"(__ret.x), "=f"(__ret.y), "=f"(__ret.z), "=f"(__ret.w)
|
|
: "l"(__ptr), "f"(__val.x), "f"(__val.y), "f"(__val.z), "f"(__val.w));
|
|
return __ret;
|
|
}
|
|
|
|
__device__ inline float4 atomicAdd_system(float4 *__ptr, float4 __val) {
|
|
float4 __ret;
|
|
__asm__(
|
|
"atom.sys.add.v4.f32 {%0, %1, %2, %3}, [%4], {%5, %6, %7, %8};"
|
|
: "=f"(__ret.x), "=f"(__ret.y), "=f"(__ret.z), "=f"(__ret.w)
|
|
: "l"(__ptr), "f"(__val.x), "f"(__val.y), "f"(__val.z), "f"(__val.w)
|
|
:);
|
|
return __ret;
|
|
}
|
|
|
|
#endif // !defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 900
|
|
#endif // CUDA_VERSION >= 11000
|
|
|
|
#endif // defined(__CLANG_CUDA_INTRINSICS_H__)
|