derek.holloway
7502bf64a4
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452 lines
16 KiB
C
452 lines
16 KiB
C
/*===----------- avxvnniint16intrin.h - AVXVNNIINT16 intrinsics-------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error \
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"Never use <avxvnniint16intrin.h> directly; include <immintrin.h> instead."
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#endif // __IMMINTRIN_H
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#ifndef __AVXVNNIINT16INTRIN_H
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#define __AVXVNNIINT16INTRIN_H
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/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
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/// corresponding unsigned 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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/// corresponding 32-bit integer in \a __W, and store the packed 32-bit
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/// results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_dpwsud_epi32(__m128i __W, __m128i __A, __m128i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPDPWSUD instruction.
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///
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/// \param __W
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/// A 128-bit vector of [4 x int].
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/// \param __A
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/// A 128-bit vector of [8 x short].
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/// \param __B
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/// A 128-bit vector of [8 x unsigned short].
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// FOR j := 0 to 3
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/// tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
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/// tmp2.dword :=
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/// SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
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/// dst.dword[j] := __W.dword[j] + tmp1 + tmp2
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/// ENDFOR
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/// dst[MAX:128] := 0
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/// \endcode
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#define _mm_dpwsud_epi32(__W, __A, __B) \
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((__m128i)__builtin_ia32_vpdpwsud128((__v4si)(__W), (__v8hi)(__A), \
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(__v8hu)(__B)))
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/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
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/// corresponding unsigned 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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/// corresponding 32-bit integer in \a __W, and store the packed 32-bit
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/// results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m256i _mm256_dpwsud_epi32(__m256i __W, __m256i __A, __m256i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPDPWSUD instruction.
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///
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/// \param __W
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/// A 256-bit vector of [8 x int].
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/// \param __A
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/// A 256-bit vector of [16 x short].
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/// \param __B
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/// A 256-bit vector of [16 x unsigned short].
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/// \returns
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/// A 256-bit vector of [8 x int].
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///
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/// \code{.operation}
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/// FOR j := 0 to 7
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/// tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
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/// tmp2.dword :=
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/// SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
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/// dst.dword[j] := __W.dword[j] + tmp1 + tmp2
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/// ENDFOR
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/// dst[MAX:256] := 0
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/// \endcode
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#define _mm256_dpwsud_epi32(__W, __A, __B) \
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((__m256i)__builtin_ia32_vpdpwsud256((__v8si)(__W), (__v16hi)(__A), \
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(__v16hu)(__B)))
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/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
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/// corresponding unsigned 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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/// corresponding 32-bit integer in \a __W with signed saturation, and store
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/// the packed 32-bit results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_dpwsuds_epi32(__m128i __W, __m128i __A, __m128i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPDPWSUDS instruction.
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///
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/// \param __W
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/// A 128-bit vector of [4 x int].
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/// \param __A
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/// A 128-bit vector of [8 x short].
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/// \param __B
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/// A 128-bit vector of [8 x unsigned short].
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// FOR j := 0 to 3
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/// tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
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/// tmp2.dword :=
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/// SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
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/// dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
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/// ENDFOR
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/// dst[MAX:128] := 0
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/// \endcode
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/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
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#define _mm_dpwsuds_epi32(__W, __A, __B) \
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((__m128i)__builtin_ia32_vpdpwsuds128((__v4si)(__W), (__v8hi)(__A), \
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(__v8hu)(__B)))
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/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a __A with
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/// corresponding unsigned 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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/// corresponding 32-bit integer in \a __W with signed saturation, and store
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/// the packed 32-bit results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m256i _mm256_dpwsuds_epi32(__m256i __W, __m256i __A, __m256i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPDPWSUDS instruction.
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///
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/// \param __W
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/// A 256-bit vector of [8 x int].
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/// \param __A
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/// A 256-bit vector of [16 x short].
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/// \param __B
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/// A 256-bit vector of [16 x unsigned short].
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/// \returns
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/// A 256-bit vector of [8 x int].
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///
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/// \code{.operation}
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/// FOR j := 0 to 7
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/// tmp1.dword := SignExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
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/// tmp2.dword :=
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/// SignExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
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/// dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
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/// ENDFOR
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/// dst[MAX:256] := 0
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/// \endcode
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#define _mm256_dpwsuds_epi32(__W, __A, __B) \
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((__m256i)__builtin_ia32_vpdpwsuds256((__v8si)(__W), (__v16hi)(__A), \
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(__v16hu)(__B)))
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/// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in \a __A
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/// with corresponding signed 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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/// corresponding 32-bit integer in \a __W, and store the packed 32-bit
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/// results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_dpbusd_epi32(__m128i __W, __m128i __A, __m128i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPDPWUSD instruction.
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///
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/// \param __W
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/// A 128-bit vector of [4 x int].
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/// \param __A
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/// A 128-bit vector of [8 x unsigned short].
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/// \param __B
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/// A 128-bit vector of [8 x short].
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// FOR j := 0 to 3
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/// tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
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/// tmp2.dword :=
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/// ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
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/// dst.dword[j] := __W.dword[j] + tmp1 + tmp2
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/// ENDFOR
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/// dst[MAX:128] := 0
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/// \endcode
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#define _mm_dpwusd_epi32(__W, __A, __B) \
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((__m128i)__builtin_ia32_vpdpwusd128((__v4si)(__W), (__v8hu)(__A), \
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(__v8hi)(__B)))
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/// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in \a __A
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/// with corresponding signed 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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/// corresponding 32-bit integer in \a __W, and store the packed 32-bit
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/// results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m256i _mm256_dpwusd_epi32(__m256i __W, __m256i __A, __m256i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPDPWUSD instruction.
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///
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/// \param __W
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/// A 256-bit vector of [8 x int].
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/// \param __A
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/// A 256-bit vector of [16 x unsigned short].
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/// \param __B
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/// A 256-bit vector of [16 x short].
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/// \returns
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/// A 256-bit vector of [8 x int].
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///
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/// \code{.operation}
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/// FOR j := 0 to 7
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/// tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
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/// tmp2.dword :=
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/// ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
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/// dst.dword[j] := __W.dword[j] + tmp1 + tmp2
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/// ENDFOR
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/// dst[MAX:256] := 0
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/// \endcode
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#define _mm256_dpwusd_epi32(__W, __A, __B) \
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((__m256i)__builtin_ia32_vpdpwusd256((__v8si)(__W), (__v16hu)(__A), \
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(__v16hi)(__B)))
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/// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in \a __A
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/// with corresponding signed 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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/// corresponding 32-bit integer in \a __W with signed saturation, and
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/// store the packed 32-bit results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_dpwusds_epi32(__m128i __W, __m128i __A, __m128i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPDPWUSDS instruction.
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///
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/// \param __W
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/// A 128-bit vector of [4 x int].
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/// \param __A
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/// A 128-bit vector of [8 x unsigned short].
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/// \param __B
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/// A 128-bit vector of [8 x short].
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// FOR j := 0 to 3
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/// tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
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/// tmp2.dword :=
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/// ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
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/// dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
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/// ENDFOR
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/// dst[MAX:128] := 0
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/// \endcode
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#define _mm_dpwusds_epi32(__W, __A, __B) \
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((__m128i)__builtin_ia32_vpdpwusds128((__v4si)(__W), (__v8hu)(__A), \
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(__v8hi)(__B)))
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/// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in \a __A
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/// with corresponding signed 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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/// corresponding 32-bit integer in \a __W with signed saturation, and
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/// store the packed 32-bit results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m256i _mm256_dpwsuds_epi32(__m256i __W, __m256i __A, __m256i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPDPWUSDS instruction.
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///
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/// \param __W
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/// A 256-bit vector of [8 x int].
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/// \param __A
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/// A 256-bit vector of [16 x unsigned short].
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/// \param __B
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/// A 256-bit vector of [16 x short].
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/// \returns
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/// A 256-bit vector of [8 x int].
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///
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/// \code{.operation}
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/// FOR j := 0 to 7
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/// tmp1.dword := ZeroExtend32(__A.word[2*j]) * SignExtend32(__B.word[2*j])
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/// tmp2.dword :=
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/// ZeroExtend32(__A.word[2*j+1]) * SignExtend32(__B.word[2*j+1])
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/// dst.dword[j] := SIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
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/// ENDFOR
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/// dst[MAX:256] := 0
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/// \endcode
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#define _mm256_dpwusds_epi32(__W, __A, __B) \
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((__m256i)__builtin_ia32_vpdpwusds256((__v8si)(__W), (__v16hu)(__A), \
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(__v16hi)(__B)))
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/// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in \a __A
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/// with corresponding unsigned 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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/// corresponding 32-bit integer in \a __W, and store the packed 32-bit
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/// results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_dpwuud_epi32(__m128i __W, __m128i __A, __m128i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPDPWUUD instruction.
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///
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/// \param __W
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/// A 128-bit vector of [4 x int].
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/// \param __A
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/// A 128-bit vector of [8 x unsigned short].
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/// \param __B
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/// A 128-bit vector of [8 x unsigned short].
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// FOR j := 0 to 3
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/// tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
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/// tmp2.dword :=
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/// ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
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/// dst.dword[j] := __W.dword[j] + tmp1 + tmp2
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/// ENDFOR
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/// dst[MAX:128] := 0
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/// \endcode
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#define _mm_dpwuud_epi32(__W, __A, __B) \
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((__m128i)__builtin_ia32_vpdpwuud128((__v4si)(__W), (__v8hu)(__A), \
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(__v8hu)(__B)))
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/// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in \a __A
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/// with corresponding unsigned 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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/// corresponding 32-bit integer in \a __W, and store the packed 32-bit
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/// results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m256i _mm256_dpwuud_epi32(__m256i __W, __m256i __A, __m256i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VPDPWUUD instruction.
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///
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/// \param __W
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/// A 256-bit vector of [8 x int].
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/// \param __A
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/// A 256-bit vector of [16 x unsigned short].
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/// \param __B
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/// A 256-bit vector of [16 x unsigned short].
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/// \returns
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/// A 256-bit vector of [8 x int].
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///
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/// \code{.operation}
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/// FOR j := 0 to 7
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/// tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
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/// tmp2.dword :=
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/// ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
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/// dst.dword[j] := __W.dword[j] + tmp1 + tmp2
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/// ENDFOR
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/// dst[MAX:256] := 0
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/// \endcode
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#define _mm256_dpwuud_epi32(__W, __A, __B) \
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((__m256i)__builtin_ia32_vpdpwuud256((__v8si)(__W), (__v16hu)(__A), \
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(__v16hu)(__B)))
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/// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in \a __A
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/// with corresponding unsigned 16-bit integers in \a __B, producing 2
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/// intermediate signed 16-bit results. Sum these 2 results with the
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|
/// corresponding 32-bit integer in \a __W with signed saturation, and store
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|
/// the packed 32-bit results in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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|
/// \code
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/// __m128i _mm_dpwsuds_epi32(__m128i __W, __m128i __A, __m128i __B)
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/// \endcode
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///
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|
/// This intrinsic corresponds to the \c VPDPWUUDS instruction.
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|
///
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|
/// \param __W
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|
/// A 128-bit vector of [4 x int].
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/// \param __A
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|
/// A 128-bit vector of [8 x unsigned short].
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|
/// \param __B
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|
/// A 128-bit vector of [8 x unsigned short].
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|
/// \returns
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|
/// A 128-bit vector of [4 x int].
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|
///
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|
/// \code{.operation}
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|
/// FOR j := 0 to 3
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|
/// tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
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|
/// tmp2.dword :=
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|
/// ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
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|
/// dst.dword[j] := UNSIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
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/// ENDFOR
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|
/// dst[MAX:128] := 0
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|
/// \endcode
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|
#define _mm_dpwuuds_epi32(__W, __A, __B) \
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|
((__m128i)__builtin_ia32_vpdpwuuds128((__v4si)(__W), (__v8hu)(__A), \
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|
(__v8hu)(__B)))
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|
|
|
/// Multiply groups of 2 adjacent pairs of unsigned 16-bit integers in \a __A
|
|
/// with corresponding unsigned 16-bit integers in \a __B, producing 2
|
|
/// intermediate signed 16-bit results. Sum these 2 results with the
|
|
/// corresponding 32-bit integer in \a __W with signed saturation, and store
|
|
/// the packed 32-bit results in \a dst.
|
|
///
|
|
/// \headerfile <immintrin.h>
|
|
///
|
|
/// \code
|
|
/// __m256i _mm256_dpwuuds_epi32(__m256i __W, __m256i __A, __m256i __B)
|
|
/// \endcode
|
|
///
|
|
/// This intrinsic corresponds to the \c VPDPWUUDS instruction.
|
|
///
|
|
/// \param __W
|
|
/// A 256-bit vector of [8 x int].
|
|
/// \param __A
|
|
/// A 256-bit vector of [16 x unsigned short].
|
|
/// \param __B
|
|
/// A 256-bit vector of [16 x unsigned short].
|
|
/// \returns
|
|
/// A 256-bit vector of [8 x int].
|
|
///
|
|
/// \code{.operation}
|
|
/// FOR j := 0 to 7
|
|
/// tmp1.dword := ZeroExtend32(__A.word[2*j]) * ZeroExtend32(__B.word[2*j])
|
|
/// tmp2.dword :=
|
|
/// ZeroExtend32(__A.word[2*j+1]) * ZeroExtend32(__B.word[2*j+1])
|
|
/// dst.dword[j] := UNSIGNED_DWORD_SATURATE(__W.dword[j] + tmp1 + tmp2)
|
|
/// ENDFOR
|
|
/// dst[MAX:256] := 0
|
|
/// \endcode
|
|
#define _mm256_dpwuuds_epi32(__W, __A, __B) \
|
|
((__m256i)__builtin_ia32_vpdpwuuds256((__v8si)(__W), (__v16hu)(__A), \
|
|
(__v16hu)(__B)))
|
|
|
|
#endif // __AVXVNNIINT16INTRIN_H
|