derek.holloway
7502bf64a4
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619 lines
26 KiB
C++
619 lines
26 KiB
C++
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -Wno-unused-value -emit-cir %s -o %t.cir
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// RUN: FileCheck --input-file=%t.cir %s
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -Wno-unused-value -emit-llvm %s -o %t-cir.ll
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// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -emit-llvm %s -o %t.ll
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// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG
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unsigned up0() {
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unsigned a = 1u;
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return +a;
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}
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// CHECK: cir.func{{.*}} @_Z3up0v() -> (!u32i{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !u32i, !cir.ptr<!u32i>, ["a", init]
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// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
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// LLVM: define{{.*}} i32 @_Z3up0v()
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// LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca i32, i64 1, align 4
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// LLVM: store i32 1, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// OGCG: define{{.*}} i32 @_Z3up0v()
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// OGCG: %[[A:.*]] = alloca i32, align 4
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// OGCG: store i32 1, ptr %[[A]], align 4
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// OGCG: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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unsigned um0() {
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unsigned a = 1u;
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return -a;
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}
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// CHECK: cir.func{{.*}} @_Z3um0v() -> (!u32i{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !u32i, !cir.ptr<!u32i>, ["a", init]
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// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
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// CHECK: %[[OUTPUT:.*]] = cir.minus %[[INPUT]]
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// LLVM: define{{.*}} i32 @_Z3um0v()
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// LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca i32, i64 1, align 4
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// LLVM: store i32 1, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// LLVM: %[[RESULT:.*]] = sub i32 0, %[[A_LOAD]]
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// OGCG: define{{.*}} i32 @_Z3um0v()
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// OGCG: %[[A:.*]] = alloca i32, align 4
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// OGCG: store i32 1, ptr %[[A]], align 4
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// OGCG: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// OGCG: %[[RESULT:.*]] = sub i32 0, %[[A_LOAD]]
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unsigned un0() {
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unsigned a = 1u;
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return ~a; // a ^ -1 , not
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}
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// CHECK: cir.func{{.*}} @_Z3un0v() -> (!u32i{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !u32i, !cir.ptr<!u32i>, ["a", init]
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// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
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// CHECK: %[[OUTPUT:.*]] = cir.not %[[INPUT]]
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// LLVM: define{{.*}} i32 @_Z3un0v()
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// LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca i32, i64 1, align 4
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// LLVM: store i32 1, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// LLVM: %[[RESULT:.*]] = xor i32 %[[A_LOAD]], -1
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// OGCG: define{{.*}} i32 @_Z3un0v()
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// OGCG: %[[A:.*]] = alloca i32, align 4
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// OGCG: store i32 1, ptr %[[A]], align 4
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// OGCG: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// OGCG: %[[RESULT:.*]] = xor i32 %[[A_LOAD]], -1
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int inc0() {
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int a = 1;
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++a;
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return a;
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}
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// CHECK: cir.func{{.*}} @_Z4inc0v() -> (!s32i{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]
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// CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
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// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
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// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
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// CHECK: %[[INCREMENTED:.*]] = cir.inc nsw %[[INPUT]]
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// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
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// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
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// LLVM: define{{.*}} i32 @_Z4inc0v()
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// LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca i32, i64 1, align 4
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// LLVM: store i32 1, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// LLVM: %[[RESULT:.*]] = add nsw i32 %[[A_LOAD]], 1
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// OGCG: define{{.*}} i32 @_Z4inc0v()
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// OGCG: %[[A:.*]] = alloca i32, align 4
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// OGCG: store i32 1, ptr %[[A]], align 4
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// OGCG: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// OGCG: %[[RESULT:.*]] = add nsw i32 %[[A_LOAD]], 1
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int dec0() {
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int a = 1;
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--a;
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return a;
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}
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// CHECK: cir.func{{.*}} @_Z4dec0v() -> (!s32i{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]
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// CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
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// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
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// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
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// CHECK: %[[DECREMENTED:.*]] = cir.dec nsw %[[INPUT]]
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// CHECK: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
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// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
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// LLVM: define{{.*}} i32 @_Z4dec0v()
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// LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca i32, i64 1, align 4
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// LLVM: store i32 1, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// LLVM: %[[RESULT:.*]] = sub nsw i32 %[[A_LOAD]], 1
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// OGCG: define{{.*}} i32 @_Z4dec0v()
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// OGCG: %[[A:.*]] = alloca i32, align 4
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// OGCG: store i32 1, ptr %[[A]], align 4
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// OGCG: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// OGCG: %[[RESULT:.*]] = add nsw i32 %[[A_LOAD]], -1
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int inc1() {
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int a = 1;
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a++;
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return a;
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}
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// CHECK: cir.func{{.*}} @_Z4inc1v() -> (!s32i{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]
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// CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
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// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
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// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
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// CHECK: %[[INCREMENTED:.*]] = cir.inc nsw %[[INPUT]]
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// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
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// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
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// LLVM: define{{.*}} i32 @_Z4inc1v()
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// LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca i32, i64 1, align 4
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// LLVM: store i32 1, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// LLVM: %[[RESULT:.*]] = add nsw i32 %[[A_LOAD]], 1
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// OGCG: define{{.*}} i32 @_Z4inc1v()
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// OGCG: %[[A:.*]] = alloca i32, align 4
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// OGCG: store i32 1, ptr %[[A]], align 4
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// OGCG: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// OGCG: %[[RESULT:.*]] = add nsw i32 %[[A_LOAD]], 1
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int dec1() {
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int a = 1;
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a--;
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return a;
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}
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// CHECK: cir.func{{.*}} @_Z4dec1v() -> (!s32i{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]
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// CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
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// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
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// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
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// CHECK: %[[DECREMENTED:.*]] = cir.dec nsw %[[INPUT]]
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// CHECK: cir.store{{.*}} %[[DECREMENTED]], %[[A]]
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// CHECK: %[[A_TO_OUTPUT:.*]] = cir.load{{.*}} %[[A]]
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// LLVM: define{{.*}} i32 @_Z4dec1v()
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// LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca i32, i64 1, align 4
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// LLVM: store i32 1, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// LLVM: %[[RESULT:.*]] = sub nsw i32 %[[A_LOAD]], 1
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// OGCG: define{{.*}} i32 @_Z4dec1v()
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// OGCG: %[[A:.*]] = alloca i32, align 4
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// OGCG: store i32 1, ptr %[[A]], align 4
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// OGCG: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// OGCG: %[[RESULT:.*]] = add nsw i32 %[[A_LOAD]], -1
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// Ensure the increment is performed after the assignment to b.
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int inc2() {
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int a = 1;
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int b = a++;
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return b;
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}
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// CHECK: cir.func{{.*}} @_Z4inc2v() -> (!s32i{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["a", init]
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// CHECK: %[[B:.*]] = cir.alloca !s32i, !cir.ptr<!s32i>, ["b", init]
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// CHECK: %[[ATMP:.*]] = cir.const #cir.int<1> : !s32i
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// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !s32i
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// CHECK: %[[ATOB:.*]] = cir.load{{.*}} %[[A]]
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// CHECK: %[[INCREMENTED:.*]] = cir.inc nsw %[[ATOB]]
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// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
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// CHECK: cir.store{{.*}} %[[ATOB]], %[[B]]
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// CHECK: %[[B_TO_OUTPUT:.*]] = cir.load{{.*}} %[[B]]
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// LLVM: define{{.*}} i32 @_Z4inc2v()
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// LLVM: %[[RV:.*]] = alloca i32, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca i32, i64 1, align 4
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// LLVM: %[[B:.*]] = alloca i32, i64 1, align 4
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// LLVM: store i32 1, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// LLVM: %[[A_INC:.*]] = add nsw i32 %[[A_LOAD]], 1
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// LLVM: store i32 %[[A_INC]], ptr %[[A]], align 4
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// LLVM: store i32 %[[A_LOAD]], ptr %[[B]], align 4
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// LLVM: %[[B_TO_OUTPUT:.*]] = load i32, ptr %[[B]], align 4
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// OGCG: define{{.*}} i32 @_Z4inc2v()
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// OGCG: %[[A:.*]] = alloca i32, align 4
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// OGCG: %[[B:.*]] = alloca i32, align 4
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// OGCG: store i32 1, ptr %[[A]], align 4
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// OGCG: %[[A_LOAD:.*]] = load i32, ptr %[[A]], align 4
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// OGCG: %[[A_INC:.*]] = add nsw i32 %[[A_LOAD]], 1
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// OGCG: store i32 %[[A_INC]], ptr %[[A]], align 4
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// OGCG: store i32 %[[A_LOAD]], ptr %[[B]], align 4
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// OGCG: %[[B_TO_OUTPUT:.*]] = load i32, ptr %[[B]], align 4
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float fpPlus() {
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float a = 1.0f;
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return +a;
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}
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// CHECK: cir.func{{.*}} @_Z6fpPlusv() -> (!cir.float{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["a", init]
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// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
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// LLVM: define{{.*}} float @_Z6fpPlusv()
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// LLVM: %[[RV:.*]] = alloca float, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca float, i64 1, align 4
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// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
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// OGCG: define{{.*}} float @_Z6fpPlusv()
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// OGCG: %[[A:.*]] = alloca float, align 4
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// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
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// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
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float fpMinus() {
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float a = 1.0f;
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return -a;
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}
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// CHECK: cir.func{{.*}} @_Z7fpMinusv() -> (!cir.float{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["a", init]
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// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
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// CHECK: %[[OUTPUT:.*]] = cir.minus %[[INPUT]]
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// LLVM: define{{.*}} float @_Z7fpMinusv()
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// LLVM: %[[RV:.*]] = alloca float, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca float, i64 1, align 4
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// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
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// LLVM: %[[RESULT:.*]] = fneg float %[[A_LOAD]]
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// OGCG: define{{.*}} float @_Z7fpMinusv()
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// OGCG: %[[A:.*]] = alloca float, align 4
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// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
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// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
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// OGCG: %[[RESULT:.*]] = fneg float %[[A_LOAD]]
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float fpPreInc() {
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float a = 1.0f;
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return ++a;
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}
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// CHECK: cir.func{{.*}} @_Z8fpPreIncv() -> (!cir.float{{.*}})
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// CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["a", init]
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// CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
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// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
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// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
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// CHECK: %[[INCREMENTED:.*]] = cir.inc %[[INPUT]]
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// LLVM: define{{.*}} float @_Z8fpPreIncv()
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// LLVM: %[[RV:.*]] = alloca float, i64 1, align 4
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// LLVM: %[[A:.*]] = alloca float, i64 1, align 4
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// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
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// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
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// LLVM: %[[RESULT:.*]] = fadd float 1.000000e+00, %[[A_LOAD]]
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// OGCG: define{{.*}} float @_Z8fpPreIncv()
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// OGCG: %[[A:.*]] = alloca float, align 4
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|
// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
|
|
// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
|
|
// OGCG: %[[RESULT:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
|
|
|
|
float fpPreDec() {
|
|
float a = 1.0f;
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|
return --a;
|
|
}
|
|
|
|
// CHECK: cir.func{{.*}} @_Z8fpPreDecv() -> (!cir.float{{.*}})
|
|
// CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["a", init]
|
|
// CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
|
|
// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
|
|
// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
|
|
// CHECK: %[[DECREMENTED:.*]] = cir.dec %[[INPUT]]
|
|
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|
// LLVM: define{{.*}} float @_Z8fpPreDecv()
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|
// LLVM: %[[RV:.*]] = alloca float, i64 1, align 4
|
|
// LLVM: %[[A:.*]] = alloca float, i64 1, align 4
|
|
// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
|
|
// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
|
|
// LLVM: %[[RESULT:.*]] = fadd float -1.000000e+00, %[[A_LOAD]]
|
|
|
|
// OGCG: define{{.*}} float @_Z8fpPreDecv()
|
|
// OGCG: %[[A:.*]] = alloca float, align 4
|
|
// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
|
|
// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
|
|
// OGCG: %[[RESULT:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
|
|
|
|
float fpPostInc() {
|
|
float a = 1.0f;
|
|
return a++;
|
|
}
|
|
|
|
// CHECK: cir.func{{.*}} @_Z9fpPostIncv() -> (!cir.float{{.*}})
|
|
// CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["a", init]
|
|
// CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
|
|
// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
|
|
// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
|
|
// CHECK: %[[INCREMENTED:.*]] = cir.inc %[[INPUT]]
|
|
|
|
// LLVM: define{{.*}} float @_Z9fpPostIncv()
|
|
// LLVM: %[[RV:.*]] = alloca float, i64 1, align 4
|
|
// LLVM: %[[A:.*]] = alloca float, i64 1, align 4
|
|
// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
|
|
// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
|
|
// LLVM: %[[RESULT:.*]] = fadd float 1.000000e+00, %[[A_LOAD]]
|
|
|
|
// OGCG: define{{.*}} float @_Z9fpPostIncv()
|
|
// OGCG: %[[A:.*]] = alloca float, align 4
|
|
// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
|
|
// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
|
|
// OGCG: %[[RESULT:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
|
|
|
|
float fpPostDec() {
|
|
float a = 1.0f;
|
|
return a--;
|
|
}
|
|
|
|
// CHECK: cir.func{{.*}} @_Z9fpPostDecv() -> (!cir.float{{.*}})
|
|
// CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["a", init]
|
|
// CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
|
|
// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
|
|
// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[A]]
|
|
// CHECK: %[[DECREMENTED:.*]] = cir.dec %[[INPUT]]
|
|
|
|
// LLVM: define{{.*}} float @_Z9fpPostDecv()
|
|
// LLVM: %[[RV:.*]] = alloca float, i64 1, align 4
|
|
// LLVM: %[[A:.*]] = alloca float, i64 1, align 4
|
|
// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
|
|
// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
|
|
// LLVM: %[[RESULT:.*]] = fadd float -1.000000e+00, %[[A_LOAD]]
|
|
|
|
// OGCG: define{{.*}} float @_Z9fpPostDecv()
|
|
// OGCG: %[[A:.*]] = alloca float, align 4
|
|
// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
|
|
// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
|
|
// OGCG: %[[RESULT:.*]] = fadd float %[[A_LOAD]], -1.000000e+00
|
|
|
|
// Ensure the increment is performed after the assignment to b.
|
|
float fpPostInc2() {
|
|
float a = 1.0f;
|
|
float b = a++;
|
|
return b;
|
|
}
|
|
|
|
// CHECK: cir.func{{.*}} @_Z10fpPostInc2v() -> (!cir.float{{.*}})
|
|
// CHECK: %[[A:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["a", init]
|
|
// CHECK: %[[B:.*]] = cir.alloca !cir.float, !cir.ptr<!cir.float>, ["b", init]
|
|
// CHECK: %[[ATMP:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.float
|
|
// CHECK: cir.store{{.*}} %[[ATMP]], %[[A]] : !cir.float
|
|
// CHECK: %[[ATOB:.*]] = cir.load{{.*}} %[[A]]
|
|
// CHECK: %[[INCREMENTED:.*]] = cir.inc %[[ATOB]]
|
|
// CHECK: cir.store{{.*}} %[[INCREMENTED]], %[[A]]
|
|
// CHECK: cir.store{{.*}} %[[ATOB]], %[[B]]
|
|
// CHECK: %[[B_TO_OUTPUT:.*]] = cir.load{{.*}} %[[B]]
|
|
|
|
// LLVM: define{{.*}} float @_Z10fpPostInc2v()
|
|
// LLVM: %[[RV:.*]] = alloca float, i64 1, align 4
|
|
// LLVM: %[[A:.*]] = alloca float, i64 1, align 4
|
|
// LLVM: %[[B:.*]] = alloca float, i64 1, align 4
|
|
// LLVM: store float 1.000000e+00, ptr %[[A]], align 4
|
|
// LLVM: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
|
|
// LLVM: %[[A_INC:.*]] = fadd float 1.000000e+00, %[[A_LOAD]]
|
|
// LLVM: store float %[[A_INC]], ptr %[[A]], align 4
|
|
// LLVM: store float %[[A_LOAD]], ptr %[[B]], align 4
|
|
// LLVM: %[[B_TO_OUTPUT:.*]] = load float, ptr %[[B]], align 4
|
|
|
|
// OGCG: define{{.*}} float @_Z10fpPostInc2v()
|
|
// OGCG: %[[A:.*]] = alloca float, align 4
|
|
// OGCG: %[[B:.*]] = alloca float, align 4
|
|
// OGCG: store float 1.000000e+00, ptr %[[A]], align 4
|
|
// OGCG: %[[A_LOAD:.*]] = load float, ptr %[[A]], align 4
|
|
// OGCG: %[[A_INC:.*]] = fadd float %[[A_LOAD]], 1.000000e+00
|
|
// OGCG: store float %[[A_INC]], ptr %[[A]], align 4
|
|
// OGCG: store float %[[A_LOAD]], ptr %[[B]], align 4
|
|
// OGCG: %[[B_TO_OUTPUT:.*]] = load float, ptr %[[B]], align 4
|
|
|
|
void chars(char c) {
|
|
// CHECK: cir.func{{.*}} @_Z5charsc
|
|
|
|
int c1 = +c;
|
|
// CHECK: %[[PROMO:.*]] = cir.cast integral %{{.+}} : !s8i -> !s32i
|
|
int c2 = -c;
|
|
// CHECK: %[[PROMO:.*]] = cir.cast integral %{{.+}} : !s8i -> !s32i
|
|
// CHECK: cir.minus nsw %[[PROMO]] : !s32i
|
|
|
|
// Chars can go through some integer promotion codegen paths even when not promoted.
|
|
// These should not have nsw attributes because the intermediate promotion makes the
|
|
// overflow defined behavior.
|
|
++c; // CHECK: cir.inc %{{.+}} : !s8i
|
|
--c; // CHECK: cir.dec %{{.+}} : !s8i
|
|
c++; // CHECK: cir.inc %{{.+}} : !s8i
|
|
c--; // CHECK: cir.dec %{{.+}} : !s8i
|
|
}
|
|
|
|
_Float16 fp16UPlus(_Float16 f) {
|
|
return +f;
|
|
}
|
|
|
|
// CHECK: cir.func{{.*}} @_Z9fp16UPlusDF16_({{.*}}) -> (!cir.f16{{.*}})
|
|
// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[F:.*]]
|
|
// CHECK: %[[PROMOTED:.*]] = cir.cast floating %[[INPUT]] : !cir.f16 -> !cir.float
|
|
// CHECK: %[[UNPROMOTED:.*]] = cir.cast floating %[[PROMOTED]] : !cir.float -> !cir.f16
|
|
|
|
// LLVM: define{{.*}} half @_Z9fp16UPlusDF16_({{.*}})
|
|
// LLVM: %[[F_LOAD:.*]] = load half, ptr %{{.*}}, align 2
|
|
// LLVM: %[[PROMOTED:.*]] = fpext half %[[F_LOAD]] to float
|
|
// LLVM: %[[UNPROMOTED:.*]] = fptrunc float %[[PROMOTED]] to half
|
|
|
|
// OGCG: define{{.*}} half @_Z9fp16UPlusDF16_({{.*}})
|
|
// OGCG: %[[F_LOAD:.*]] = load half, ptr %{{.*}}, align 2
|
|
// OGCG: %[[PROMOTED:.*]] = fpext half %[[F_LOAD]] to float
|
|
// OGCG: %[[UNPROMOTED:.*]] = fptrunc float %[[PROMOTED]] to half
|
|
|
|
_Float16 fp16UMinus(_Float16 f) {
|
|
return -f;
|
|
}
|
|
|
|
// CHECK: cir.func{{.*}} @_Z10fp16UMinusDF16_({{.*}}) -> (!cir.f16{{.*}})
|
|
// CHECK: %[[INPUT:.*]] = cir.load{{.*}} %[[F:.*]]
|
|
// CHECK: %[[PROMOTED:.*]] = cir.cast floating %[[INPUT]] : !cir.f16 -> !cir.float
|
|
// CHECK: %[[RESULT:.*]] = cir.minus %[[PROMOTED]]
|
|
// CHECK: %[[UNPROMOTED:.*]] = cir.cast floating %[[RESULT]] : !cir.float -> !cir.f16
|
|
|
|
// LLVM: define{{.*}} half @_Z10fp16UMinusDF16_({{.*}})
|
|
// LLVM: %[[F_LOAD:.*]] = load half, ptr %{{.*}}, align 2
|
|
// LLVM: %[[PROMOTED:.*]] = fpext half %[[F_LOAD]] to float
|
|
// LLVM: %[[RESULT:.*]] = fneg float %[[PROMOTED]]
|
|
// LLVM: %[[UNPROMOTED:.*]] = fptrunc float %[[RESULT]] to half
|
|
|
|
// OGCG: define{{.*}} half @_Z10fp16UMinusDF16_({{.*}})
|
|
// OGCG: %[[F_LOAD:.*]] = load half, ptr %{{.*}}, align 2
|
|
// OGCG: %[[PROMOTED:.*]] = fpext half %[[F_LOAD]] to float
|
|
// OGCG: %[[RESULT:.*]] = fneg float %[[PROMOTED]]
|
|
// OGCG: %[[UNPROMOTED:.*]] = fptrunc float %[[RESULT]] to half
|
|
|
|
void test_logical_not() {
|
|
int a = 5;
|
|
a = !a;
|
|
bool b = false;
|
|
b = !b;
|
|
float c = 2.0f;
|
|
c = !c;
|
|
int *p = 0;
|
|
b = !p;
|
|
double d = 3.0;
|
|
b = !d;
|
|
}
|
|
|
|
// CHECK: cir.func{{.*}} @_Z16test_logical_notv()
|
|
// CHECK: %[[A:.*]] = cir.load{{.*}} %[[A_ADDR:.*]] : !cir.ptr<!s32i>, !s32i
|
|
// CHECK: %[[A_BOOL:.*]] = cir.cast int_to_bool %[[A]] : !s32i -> !cir.bool
|
|
// CHECK: %[[A_NOT:.*]] = cir.not %[[A_BOOL]] : !cir.bool
|
|
// CHECK: %[[A_CAST:.*]] = cir.cast bool_to_int %[[A_NOT]] : !cir.bool -> !s32i
|
|
// CHECK: cir.store{{.*}} %[[A_CAST]], %[[A_ADDR]] : !s32i, !cir.ptr<!s32i>
|
|
// CHECK: %[[B:.*]] = cir.load{{.*}} %[[B_ADDR:.*]] : !cir.ptr<!cir.bool>, !cir.bool
|
|
// CHECK: %[[B_NOT:.*]] = cir.not %[[B]] : !cir.bool
|
|
// CHECK: cir.store{{.*}} %[[B_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr<!cir.bool>
|
|
// CHECK: %[[C:.*]] = cir.load{{.*}} %[[C_ADDR:.*]] : !cir.ptr<!cir.float>, !cir.float
|
|
// CHECK: %[[C_BOOL:.*]] = cir.cast float_to_bool %[[C]] : !cir.float -> !cir.bool
|
|
// CHECK: %[[C_NOT:.*]] = cir.not %[[C_BOOL]] : !cir.bool
|
|
// CHECK: %[[C_CAST:.*]] = cir.cast bool_to_float %[[C_NOT]] : !cir.bool -> !cir.float
|
|
// CHECK: cir.store{{.*}} %[[C_CAST]], %[[C_ADDR]] : !cir.float, !cir.ptr<!cir.float>
|
|
// CHECK: %[[P:.*]] = cir.load{{.*}} %[[P_ADDR:.*]] : !cir.ptr<!cir.ptr<!s32i>>, !cir.ptr<!s32i>
|
|
// CHECK: %[[P_BOOL:.*]] = cir.cast ptr_to_bool %[[P]] : !cir.ptr<!s32i> -> !cir.bool
|
|
// CHECK: %[[P_NOT:.*]] = cir.not %[[P_BOOL]] : !cir.bool
|
|
// CHECK: cir.store{{.*}} %[[P_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr<!cir.bool>
|
|
// CHECK: %[[D:.*]] = cir.load{{.*}} %[[D_ADDR:.*]] : !cir.ptr<!cir.double>, !cir.double
|
|
// CHECK: %[[D_BOOL:.*]] = cir.cast float_to_bool %[[D]] : !cir.double -> !cir.bool
|
|
// CHECK: %[[D_NOT:.*]] = cir.not %[[D_BOOL]] : !cir.bool
|
|
// CHECK: cir.store{{.*}} %[[D_NOT]], %[[B_ADDR]] : !cir.bool, !cir.ptr<!cir.bool>
|
|
|
|
// LLVM: define{{.*}} void @_Z16test_logical_notv()
|
|
// LLVM: %[[A:.*]] = load i32, ptr %[[A_ADDR:.*]], align 4
|
|
// LLVM: %[[A_BOOL:.*]] = icmp ne i32 %[[A]], 0
|
|
// LLVM: %[[A_NOT:.*]] = xor i1 %[[A_BOOL]], true
|
|
// LLVM: %[[A_CAST:.*]] = zext i1 %[[A_NOT]] to i32
|
|
// LLVM: store i32 %[[A_CAST]], ptr %[[A_ADDR]], align 4
|
|
// LLVM: %[[B:.*]] = load i8, ptr %[[B_ADDR:.*]], align 1
|
|
// LLVM: %[[B_BOOL:.*]] = trunc i8 %[[B]] to i1
|
|
// LLVM: %[[B_NOT:.*]] = xor i1 %[[B_BOOL]], true
|
|
// LLVM: %[[B_CAST:.*]] = zext i1 %[[B_NOT]] to i8
|
|
// LLVM: store i8 %[[B_CAST]], ptr %[[B_ADDR]], align 1
|
|
// LLVM: %[[C:.*]] = load float, ptr %[[C_ADDR:.*]], align 4
|
|
// LLVM: %[[C_BOOL:.*]] = fcmp une float %[[C]], 0.000000e+00
|
|
// LLVM: %[[C_NOT:.*]] = xor i1 %[[C_BOOL]], true
|
|
// LLVM: %[[C_CAST:.*]] = uitofp i1 %[[C_NOT]] to float
|
|
// LLVM: store float %[[C_CAST]], ptr %[[C_ADDR]], align 4
|
|
// LLVM: %[[P:.*]] = load ptr, ptr %[[P_ADDR:.*]], align 8
|
|
// LLVM: %[[P_BOOL:.*]] = icmp ne ptr %[[P]], null
|
|
// LLVM: %[[P_NOT:.*]] = xor i1 %[[P_BOOL]], true
|
|
// LLVM: %[[P_CAST:.*]] = zext i1 %[[P_NOT]] to i8
|
|
// LLVM: store i8 %[[P_CAST]], ptr %[[B_ADDR]], align 1
|
|
// LLVM: %[[D:.*]] = load double, ptr %[[D_ADDR:.*]], align 8
|
|
// LLVM: %[[D_BOOL:.*]] = fcmp une double %[[D]], 0.000000e+00
|
|
// LLVM: %[[D_NOT:.*]] = xor i1 %[[D_BOOL]], true
|
|
// LLVM: %[[D_CAST:.*]] = zext i1 %[[D_NOT]] to i8
|
|
// LLVM: store i8 %[[D_CAST]], ptr %[[B_ADDR]], align 1
|
|
|
|
// OGCG: define{{.*}} void @_Z16test_logical_notv()
|
|
// OGCG: %[[A:.*]] = load i32, ptr %[[A_ADDR:.*]], align 4
|
|
// OGCG: %[[A_BOOL:.*]] = icmp ne i32 %[[A]], 0
|
|
// OGCG: %[[A_NOT:.*]] = xor i1 %[[A_BOOL]], true
|
|
// OGCG: %[[A_CAST:.*]] = zext i1 %[[A_NOT]] to i32
|
|
// OGCG: store i32 %[[A_CAST]], ptr %[[A_ADDR]], align 4
|
|
// OGCG: %[[B:.*]] = load i8, ptr %[[B_ADDR:.*]], align 1
|
|
// OGCG: %[[B_BOOL:.*]] = icmp ne i8 %[[B]], 0
|
|
// OGCG: %[[B_NOT:.*]] = xor i1 %[[B_BOOL]], true
|
|
// OGCG: %[[B_CAST:.*]] = zext i1 %[[B_NOT]] to i8
|
|
// OGCG: store i8 %[[B_CAST]], ptr %[[B_ADDR]], align 1
|
|
// OGCG: %[[C:.*]] = load float, ptr %[[C_ADDR:.*]], align 4
|
|
// OGCG: %[[C_BOOL:.*]] = fcmp une float %[[C]], 0.000000e+00
|
|
// OGCG: %[[C_NOT:.*]] = xor i1 %[[C_BOOL]], true
|
|
// OGCG: %[[C_CAST:.*]] = uitofp i1 %[[C_NOT]] to float
|
|
// OGCG: store float %[[C_CAST]], ptr %[[C_ADDR]], align 4
|
|
// OGCG: %[[P:.*]] = load ptr, ptr %[[P_ADDR:.*]], align 8
|
|
// OGCG: %[[P_BOOL:.*]] = icmp ne ptr %[[P]], null
|
|
// OGCG: %[[P_NOT:.*]] = xor i1 %[[P_BOOL]], true
|
|
// OGCG: %[[P_CAST:.*]] = zext i1 %[[P_NOT]] to i8
|
|
// OGCG: store i8 %[[P_CAST]], ptr %[[B_ADDR]], align 1
|
|
// OGCG: %[[D:.*]] = load double, ptr %[[D_ADDR:.*]], align 8
|
|
// OGCG: %[[D_BOOL:.*]] = fcmp une double %[[D]], 0.000000e+00
|
|
// OGCG: %[[D_NOT:.*]] = xor i1 %[[D_BOOL]], true
|
|
// OGCG: %[[D_CAST:.*]] = zext i1 %[[D_NOT]] to i8
|
|
// OGCG: store i8 %[[D_CAST]], ptr %[[B_ADDR]], align 1
|
|
|
|
void f16NestedUPlus() {
|
|
_Float16 a;
|
|
_Float16 b = +(+a);
|
|
}
|
|
|
|
// CHECK: cir.func{{.*}} @_Z14f16NestedUPlusv()
|
|
// CHECK: %[[A_ADDR:.*]] = cir.alloca !cir.f16, !cir.ptr<!cir.f16>, ["a"]
|
|
// CHECK: %[[B_ADDR:.*]] = cir.alloca !cir.f16, !cir.ptr<!cir.f16>, ["b", init]
|
|
// CHECK: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!cir.f16>, !cir.f16
|
|
// CHECK: %[[A_F32:.*]] = cir.cast floating %[[TMP_A]] : !cir.f16 -> !cir.float
|
|
// CHECK: %[[RESULT:.*]] = cir.cast floating %[[A_F32]] : !cir.float -> !cir.f16
|
|
// CHECK: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.f16, !cir.ptr<!cir.f16>
|
|
|
|
// LLVM: define{{.*}} void @_Z14f16NestedUPlusv()
|
|
// LLVM: %[[A_ADDR:.*]] = alloca half, i64 1, align 2
|
|
// LLVM: %[[B_ADDR:.*]] = alloca half, i64 1, align 2
|
|
// LLVM: %[[TMP_A:.*]] = load half, ptr %[[A_ADDR]], align 2
|
|
// LLVM: %[[RESULT_F32:.*]] = fpext half %[[TMP_A]] to float
|
|
// LLVM: %[[RESULT:.*]] = fptrunc float %[[RESULT_F32]] to half
|
|
// LLVM: store half %[[RESULT]], ptr %[[B_ADDR]], align 2
|
|
|
|
// OGCG: define{{.*}} void @_Z14f16NestedUPlusv()
|
|
// OGCG: %[[A_ADDR:.*]] = alloca half, align 2
|
|
// OGCG: %[[B_ADDR:.*]] = alloca half, align 2
|
|
// OGCG: %[[TMP_A:.*]] = load half, ptr %[[A_ADDR]], align 2
|
|
// OGCG: %[[RESULT_F32:.*]] = fpext half %[[TMP_A]] to float
|
|
// OGCG: %[[RESULT:.*]] = fptrunc float %[[RESULT_F32]] to half
|
|
// OGCG: store half %[[RESULT]], ptr %[[B_ADDR]], align 2
|
|
|
|
void f16NestedUMinus() {
|
|
_Float16 a;
|
|
_Float16 b = -(-a);
|
|
}
|
|
|
|
// CHECK: cir.func{{.*}} @_Z15f16NestedUMinusv()
|
|
// CHECK: %[[A_ADDR:.*]] = cir.alloca !cir.f16, !cir.ptr<!cir.f16>, ["a"]
|
|
// CHECK: %[[B_ADDR:.*]] = cir.alloca !cir.f16, !cir.ptr<!cir.f16>, ["b", init]
|
|
// CHECK: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr<!cir.f16>, !cir.f16
|
|
// CHECK: %[[A_F32:.*]] = cir.cast floating %[[TMP_A]] : !cir.f16 -> !cir.float
|
|
// CHECK: %[[A_MINUS:.*]] = cir.minus %[[A_F32]] : !cir.float
|
|
// CHECK: %[[RESULT_F32:.*]] = cir.minus %[[A_MINUS]] : !cir.float
|
|
// CHECK: %[[RESULT:.*]] = cir.cast floating %[[RESULT_F32]] : !cir.float -> !cir.f16
|
|
// CHECK: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.f16, !cir.ptr<!cir.f16>
|
|
|
|
// LLVM: define{{.*}} void @_Z15f16NestedUMinusv()
|
|
// LLVM: %[[A_ADDR:.*]] = alloca half, i64 1, align 2
|
|
// LLVM: %[[B_ADDR:.*]] = alloca half, i64 1, align 2
|
|
// LLVM: %[[TMP_A:.*]] = load half, ptr %[[A_ADDR]], align 2
|
|
// LLVM: %[[A_F32:.*]] = fpext half %[[TMP_A]] to float
|
|
// LLVM: %[[A_MINUS:.*]] = fneg float %[[A_F32]]
|
|
// LLVM: %[[RESULT_F32:.*]] = fneg float %[[A_MINUS]]
|
|
// LLVM: %[[RESULT:.*]] = fptrunc float %[[RESULT_F32]] to half
|
|
// LLVM: store half %[[RESULT]], ptr %[[B_ADDR]], align 2
|
|
|
|
// OGCG: define{{.*}} void @_Z15f16NestedUMinusv()
|
|
// OGCG: %[[A_ADDR:.*]] = alloca half, align 2
|
|
// OGCG: %[[B_ADDR:.*]] = alloca half, align 2
|
|
// OGCG: %[[TMP_A:.*]] = load half, ptr %[[A_ADDR]], align 2
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// OGCG: %[[A_F32:.*]] = fpext half %[[TMP_A]] to float
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// OGCG: %[[A_MINUS:.*]] = fneg float %[[A_F32]]
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// OGCG: %[[RESULT_F32:.*]] = fneg float %[[A_MINUS]]
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// OGCG: %[[RESULT:.*]] = fptrunc float %[[RESULT_F32]] to half
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// OGCG: store half %[[RESULT]], ptr %[[B_ADDR]], align 2
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