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46 lines
2.0 KiB
Plaintext
46 lines
2.0 KiB
Plaintext
// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -target-cpu sm_70 \
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// RUN: -target-feature +ptx62 -fclangir -fcuda-is-device \
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// RUN: -emit-cir %s -o %t.cir
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// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
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// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -target-cpu sm_70 \
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// RUN: -target-feature +ptx62 -fclangir -fcuda-is-device \
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// RUN: -emit-llvm %s -o %t-cir.ll
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// RUN: FileCheck --check-prefix=LLVM --input-file=%t-cir.ll %s
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// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -target-cpu sm_70 \
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// RUN: -target-feature +ptx62 -fcuda-is-device \
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// RUN: -emit-llvm %s -o %t.ll
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// RUN: FileCheck --check-prefix=OGCG --input-file=%t.ll %s
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#define __device__ __attribute__((device))
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// Tests CIR/LLVM lowering for NVPTX CTA-level sync barrier builtins.
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// Mirrors the relevant slices of clang/test/CodeGen/builtins-nvptx.c and
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// clang/test/CodeGen/builtins-nvptx-ptx60.cu.
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// CIR-LABEL: cir.func {{.*}} @_Z9nvvm_syncj
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// LLVM-LABEL: define{{.*}} void @_Z9nvvm_syncj(
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// OGCG-LABEL: define{{.*}} void @_Z9nvvm_syncj(
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__device__ void nvvm_sync(unsigned mask) {
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// CIR: cir.call_llvm_intrinsic "nvvm.barrier.cta.sync.aligned.all"
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// LLVM: call void @llvm.nvvm.barrier.cta.sync.aligned.all(i32 0)
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// OGCG: call void @llvm.nvvm.barrier.cta.sync.aligned.all(i32 0)
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__nvvm_bar_sync(0);
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// CIR: cir.call_llvm_intrinsic "nvvm.barrier.cta.sync.aligned.all"
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// LLVM: call void @llvm.nvvm.barrier.cta.sync.aligned.all(i32 0)
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// OGCG: call void @llvm.nvvm.barrier.cta.sync.aligned.all(i32 0)
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__syncthreads();
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// CIR: cir.call_llvm_intrinsic "nvvm.barrier.cta.sync.all"
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// LLVM: call void @llvm.nvvm.barrier.cta.sync.all(i32 %{{.*}})
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// OGCG: call void @llvm.nvvm.barrier.cta.sync.all(i32 %{{.*}})
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__nvvm_barrier_sync(mask);
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// CIR: cir.call_llvm_intrinsic "nvvm.barrier.cta.sync.count"
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// LLVM: call void @llvm.nvvm.barrier.cta.sync.count(i32 %{{.*}}, i32 0)
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// OGCG: call void @llvm.nvvm.barrier.cta.sync.count(i32 %{{.*}}, i32 0)
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__nvvm_barrier_sync_cnt(mask, 0);
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}
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