derek.holloway
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45 lines
1.9 KiB
Plaintext
45 lines
1.9 KiB
Plaintext
// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -target-cpu sm_90 \
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// RUN: -target-feature +ptx80 -fclangir -fcuda-is-device \
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// RUN: -emit-cir %s -o %t.cir
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// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
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// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -target-cpu sm_90 \
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// RUN: -target-feature +ptx80 -fclangir -fcuda-is-device \
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// RUN: -emit-llvm %s -o %t-cir.ll
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// RUN: FileCheck --check-prefix=LLVM --input-file=%t-cir.ll %s
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// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -target-cpu sm_90 \
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// RUN: -target-feature +ptx80 -fcuda-is-device \
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// RUN: -emit-llvm %s -o %t.ll
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// RUN: FileCheck --check-prefix=OGCG --input-file=%t.ll %s
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#define __global__ __attribute__((global))
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// Tests CIR/LLVM lowering for sm_90 cluster barrier and fence builtins.
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// Mirrors the relevant slice of clang/test/CodeGenCUDA/builtins-sm90.cu.
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// CIR-LABEL: cir.func {{.*}} @_Z6kernelv
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// LLVM-LABEL: define{{.*}} void @_Z6kernelv(
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// OGCG-LABEL: define{{.*}} void @_Z6kernelv(
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__global__ void kernel() {
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// CIR: cir.call_llvm_intrinsic "nvvm.barrier.cluster.arrive"
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// LLVM: call void @llvm.nvvm.barrier.cluster.arrive()
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// OGCG: call void @llvm.nvvm.barrier.cluster.arrive()
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__nvvm_barrier_cluster_arrive();
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// CIR: cir.call_llvm_intrinsic "nvvm.barrier.cluster.arrive.relaxed"
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// LLVM: call void @llvm.nvvm.barrier.cluster.arrive.relaxed()
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// OGCG: call void @llvm.nvvm.barrier.cluster.arrive.relaxed()
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__nvvm_barrier_cluster_arrive_relaxed();
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// CIR: cir.call_llvm_intrinsic "nvvm.barrier.cluster.wait"
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// LLVM: call void @llvm.nvvm.barrier.cluster.wait()
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// OGCG: call void @llvm.nvvm.barrier.cluster.wait()
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__nvvm_barrier_cluster_wait();
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// CIR: cir.call_llvm_intrinsic "nvvm.fence.sc.cluster"
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// LLVM: call void @llvm.nvvm.fence.sc.cluster()
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// OGCG: call void @llvm.nvvm.fence.sc.cluster()
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__nvvm_fence_sc_cluster();
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}
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