derek.holloway
7502bf64a4
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43 lines
1.5 KiB
C
43 lines
1.5 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1_cg_arm64_neon -target-feature +bf16 -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s
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// REQUIRES: aarch64-registered-target || arm-registered-target
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#include <arm_neon.h>
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// CHECK-LABEL: @test_vcreate_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A:%.*]] to <4 x bfloat>
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// CHECK-NEXT: ret <4 x bfloat> [[TMP0]]
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//
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bfloat16x4_t test_vcreate_bf16(uint64_t a) {
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return vcreate_bf16(a);
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}
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// CHECK-LABEL: @test_vcombine_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x bfloat> [[LOW:%.*]], <4 x bfloat> [[HIGH:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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// CHECK-NEXT: ret <8 x bfloat> [[SHUFFLE_I]]
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//
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bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) {
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return vcombine_bf16(low, high);
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}
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// CHECK-LABEL: @test_vset_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <4 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 1
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// CHECK-NEXT: ret <4 x bfloat> [[VSET_LANE]]
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//
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bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) {
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return vset_lane_bf16(a, v, 1);
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}
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// CHECK-LABEL: @test_vsetq_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <8 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 7
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// CHECK-NEXT: ret <8 x bfloat> [[VSET_LANE]]
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//
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bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) {
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return vsetq_lane_bf16(a, v, 7);
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}
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