derek.holloway
7502bf64a4
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102 lines
5.8 KiB
C
102 lines
5.8 KiB
C
// REQUIRES: aarch64-registered-target || arm-registered-target
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// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -flax-vector-conversions=none -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM
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// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=ALL,LLVM %}
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// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -disable-O0-optnone -flax-vector-conversions=none -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR %}
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#include <arm_neon.h>
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//===------------------------------------------------------===//
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// 2.7.2.4 Set all lanes to the same value
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//===------------------------------------------------------===//
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// ALL-LABEL: @test_vdup_n_f16(
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float16x4_t test_vdup_n_f16(float16_t a) {
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// CIR: cir.vec.create(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : !cir.f16, !cir.f16, !cir.f16, !cir.f16) : !cir.vector<4 x !cir.f16>
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// LLVM-SAME: half noundef [[A:%.*]])
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// LLVM: [[VECINIT:%.*]] = insertelement <4 x half> poison, half [[A]], i{{32|64}} 0
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// LLVM-NEXT: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[A]], i{{32|64}} 1
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// LLVM-NEXT: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[A]], i{{32|64}} 2
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// LLVM-NEXT: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[A]], i{{32|64}} 3
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// LLVM: ret <4 x half> [[VECINIT3]]
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return vdup_n_f16(a);
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}
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// ALL-LABEL: @test_vdupq_n_f16(
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float16x8_t test_vdupq_n_f16(float16_t a) {
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// CIR: cir.vec.create(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : !cir.f16, !cir.f16, !cir.f16, !cir.f16, !cir.f16, !cir.f16, !cir.f16, !cir.f16) : !cir.vector<8 x !cir.f16>
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// LLVM-SAME: half noundef [[A:%.*]])
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// LLVM: [[VECINIT:%.*]] = insertelement <8 x half> poison, half [[A]], i{{32|64}} 0
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// LLVM-NEXT: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[A]], i{{32|64}} 1
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// LLVM-NEXT: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[A]], i{{32|64}} 2
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// LLVM-NEXT: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[A]], i{{32|64}} 3
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// LLVM-NEXT: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[A]], i{{32|64}} 4
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// LLVM-NEXT: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[A]], i{{32|64}} 5
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// LLVM-NEXT: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[A]], i{{32|64}} 6
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// LLVM-NEXT: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[A]], i{{32|64}} 7
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// LLVM: ret <8 x half> [[VECINIT7]]
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return vdupq_n_f16(a);
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}
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// ALL-LABEL: @test_vdup_lane_f16(
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float16x4_t test_vdup_lane_f16(float16x4_t a) {
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// CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !cir.f16>) [#cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !cir.f16>
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// LLVM-SAME: <4 x half> noundef [[A:%.*]])
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// LLVM: [[LANE:%.*]] = shufflevector <4 x half> {{.*}}, <4 x half> {{.*}}, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
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// LLVM: ret <4 x half> [[LANE]]
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return vdup_lane_f16(a, 3);
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}
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// ALL-LABEL: @test_vdupq_lane_f16(
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float16x8_t test_vdupq_lane_f16(float16x4_t a) {
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// CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !cir.f16>) [#cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i, #cir.int<3> : !s32i] : !cir.vector<8 x !cir.f16>
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// LLVM-SAME: <4 x half> noundef [[A:%.*]])
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// LLVM: [[LANE:%.*]] = shufflevector <4 x half> {{.*}}, <4 x half> {{.*}}, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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// LLVM: ret <8 x half> [[LANE]]
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return vdupq_lane_f16(a, 3);
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}
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// ALL-LABEL: @test_vdup_laneq_f16(
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float16x4_t test_vdup_laneq_f16(float16x8_t a) {
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// CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !cir.f16>) [#cir.int<1> : !s32i, #cir.int<1> : !s32i, #cir.int<1> : !s32i, #cir.int<1> : !s32i] : !cir.vector<4 x !cir.f16>
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// LLVM-SAME: <8 x half> noundef [[A:%.*]])
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// LLVM: [[LANE:%.*]] = shufflevector <8 x half> {{.*}}, <8 x half> {{.*}}, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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// LLVM: ret <4 x half> [[LANE]]
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return vdup_laneq_f16(a, 1);
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}
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// ALL-LABEL: @test_vdupq_laneq_f16(
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float16x8_t test_vdupq_laneq_f16(float16x8_t a) {
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// CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !cir.f16>) [#cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !cir.f16>
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// LLVM-SAME: <8 x half> noundef [[A:%.*]])
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// LLVM: [[LANE:%.*]] = shufflevector <8 x half> {{.*}}, <8 x half> {{.*}}, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
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// LLVM: ret <8 x half> [[LANE]]
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return vdupq_laneq_f16(a, 7);
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}
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// ALL-LABEL: @test_vduph_lane_f16(
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float16_t test_vduph_lane_f16(float16x4_t vec) {
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// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !cir.f16>
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// LLVM-SAME: <4 x half> {{.*}}[[VEC:%.*]])
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// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x half> [[VEC]], i32 3
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// LLVM: ret half [[VGET_LANE]]
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return vduph_lane_f16(vec, 3);
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}
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// ALL-LABEL: @test_vduph_laneq_f16(
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float16_t test_vduph_laneq_f16(float16x8_t vec) {
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// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !cir.f16>
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// LLVM-SAME: <8 x half> {{.*}}[[VEC:%.*]])
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// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x half> [[VEC]], i32 7
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// LLVM: ret half [[VGETQ_LANE]]
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return vduph_laneq_f16(vec, 7);
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}
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