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TheRock/compiler/amd-llvm/clang/test/CodeGen/PowerPC/builtins-ppc-deeply-compressed-weights.c
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +future-vector \
// RUN: -target-feature +vsx -target-feature +isa-future-instructions \
// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +future-vector \
// RUN: -target-feature +vsx -target-feature +isa-future-instructions \
// RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s
// AI Assisted.
#include <altivec.h>
vector unsigned char vuca, vucb;
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_uncompresshn(
// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[__B_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: store <16 x i8> [[TMP1]], ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.vucmprhn(<16 x i8> [[TMP2]], <16 x i8> [[TMP3]])
// CHECK-NEXT: ret <16 x i8> [[TMP4]]
//
vector unsigned char test_vec_uncompresshn(void) {
return vec_uncompresshn(vuca, vucb);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_uncompressln(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[__B_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: store <16 x i8> [[TMP1]], ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.vucmprln(<16 x i8> [[TMP2]], <16 x i8> [[TMP3]])
// CHECK-NEXT: ret <16 x i8> [[TMP4]]
//
vector unsigned char test_vec_uncompressln(void) {
return vec_uncompressln(vuca, vucb);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_uncompresshb(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[__B_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: store <16 x i8> [[TMP1]], ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.vucmprhb(<16 x i8> [[TMP2]], <16 x i8> [[TMP3]])
// CHECK-NEXT: ret <16 x i8> [[TMP4]]
//
vector unsigned char test_vec_uncompresshb(void) {
return vec_uncompresshb(vuca, vucb);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_uncompresslb(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[__B_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: store <16 x i8> [[TMP1]], ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.vucmprlb(<16 x i8> [[TMP2]], <16 x i8> [[TMP3]])
// CHECK-NEXT: ret <16 x i8> [[TMP4]]
//
vector unsigned char test_vec_uncompresslb(void) {
return vec_uncompresslb(vuca, vucb);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_uncompresshh(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[__B_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: store <16 x i8> [[TMP1]], ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.vucmprhh(<16 x i8> [[TMP2]], <16 x i8> [[TMP3]])
// CHECK-NEXT: ret <16 x i8> [[TMP4]]
//
vector unsigned char test_vec_uncompresshh(void) {
return vec_uncompresshh(vuca, vucb);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_uncompresslh(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[__B_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @vucb, align 16
// CHECK-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: store <16 x i8> [[TMP1]], ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr [[__B_ADDR_I]], align 16
// CHECK-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.ppc.altivec.vucmprlh(<16 x i8> [[TMP2]], <16 x i8> [[TMP3]])
// CHECK-NEXT: ret <16 x i8> [[TMP4]]
//
vector unsigned char test_vec_uncompresslh(void) {
return vec_uncompresslh(vuca, vucb);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_unpack_hsn_to_byte(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.altivec.vupkhsntob(<16 x i8> [[TMP1]])
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
vector unsigned char test_vec_unpack_hsn_to_byte(void) {
return vec_unpack_hsn_to_byte(vuca);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_unpack_lsn_to_byte(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[__A_ADDR_I:%.*]] = alloca <16 x i8>, align 16
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: store <16 x i8> [[TMP0]], ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[__A_ADDR_I]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.ppc.altivec.vupklsntob(<16 x i8> [[TMP1]])
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
vector unsigned char test_vec_unpack_lsn_to_byte(void) {
return vec_unpack_lsn_to_byte(vuca);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_unpack_int4_to_bf16(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.ppc.altivec.vupkint4tobf16(<16 x i8> [[TMP0]], i32 2)
// CHECK-NEXT: ret <16 x i8> [[TMP1]]
//
vector unsigned char test_vec_unpack_int4_to_bf16(void) {
return vec_unpack_int4_to_bf16(vuca, 2);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_unpack_int8_to_bf16(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.ppc.altivec.vupkint8tobf16(<16 x i8> [[TMP0]], i32 1)
// CHECK-NEXT: ret <16 x i8> [[TMP1]]
//
vector unsigned char test_vec_unpack_int8_to_bf16(void) {
return vec_unpack_int8_to_bf16(vuca, 1);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_unpack_int4_to_fp32(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.ppc.altivec.vupkint4tofp32(<16 x i8> [[TMP0]], i32 5)
// CHECK-NEXT: ret <16 x i8> [[TMP1]]
//
vector unsigned char test_vec_unpack_int4_to_fp32(void) {
return vec_unpack_int4_to_fp32(vuca, 5);
}
// CHECK-LABEL: define dso_local <16 x i8> @test_vec_unpack_int8_to_fp32(
// CHECK-SAME: ) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @vuca, align 16
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i8> @llvm.ppc.altivec.vupkint8tofp32(<16 x i8> [[TMP0]], i32 3)
// CHECK-NEXT: ret <16 x i8> [[TMP1]]
//
vector unsigned char test_vec_unpack_int8_to_fp32(void) {
return vec_unpack_int8_to_fp32(vuca, 3);
}
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