derek.holloway
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37 lines
1.7 KiB
C
37 lines
1.7 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -emit-llvm -target-feature +v \
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// RUN: %s -o - \
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// RUN: | FileCheck %s
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#include <riscv_vector.h>
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#define __rvv_generic \
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static inline __attribute__((__always_inline__, __nodebug__))
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__rvv_generic
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__attribute__((clang_builtin_alias(__builtin_rvv_vadd_vv)))
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vint8m1_t vadd_generic (vint8m1_t op0, vint8m1_t op1, size_t op2);
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// CHECK-LABEL: @test(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[OP0_ADDR:%.*]] = alloca <vscale x 8 x i8>, align 1
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// CHECK-NEXT: [[OP1_ADDR:%.*]] = alloca <vscale x 8 x i8>, align 1
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// CHECK-NEXT: [[VL_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[RET:%.*]] = alloca <vscale x 8 x i8>, align 1
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// CHECK-NEXT: store <vscale x 8 x i8> [[OP0:%.*]], ptr [[OP0_ADDR]], align 1
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// CHECK-NEXT: store <vscale x 8 x i8> [[OP1:%.*]], ptr [[OP1_ADDR]], align 1
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// CHECK-NEXT: store i64 [[VL:%.*]], ptr [[VL_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 8 x i8>, ptr [[OP0_ADDR]], align 1
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// CHECK-NEXT: [[TMP1:%.*]] = load <vscale x 8 x i8>, ptr [[OP1_ADDR]], align 1
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// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[VL_ADDR]], align 8
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// CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> [[TMP0]], <vscale x 8 x i8> [[TMP1]], i64 [[TMP2]])
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// CHECK-NEXT: store <vscale x 8 x i8> [[TMP3]], ptr [[RET]], align 1
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// CHECK-NEXT: [[TMP4:%.*]] = load <vscale x 8 x i8>, ptr [[RET]], align 1
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// CHECK-NEXT: ret <vscale x 8 x i8> [[TMP4]]
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//
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vint8m1_t test(vint8m1_t op0, vint8m1_t op1, size_t vl) {
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vint8m1_t ret = vadd_generic(op0, op1, vl);
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return ret;
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}
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