derek.holloway
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73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple riscv32 -target-feature +zbc -emit-llvm %s -o - \
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// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
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// RUN: | FileCheck %s -check-prefix=RV32ZBC
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// RUN: %clang_cc1 -triple riscv64 -target-feature +zbc -emit-llvm %s -o - \
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// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
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// RUN: | FileCheck %s -check-prefix=RV64ZBC
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#include <riscv_bitmanip.h>
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#if __riscv_xlen == 64
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// RV64ZBC-LABEL: @clmul_64(
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// RV64ZBC-NEXT: entry:
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// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.clmul.i64(i64 [[A:%.*]], i64 [[B:%.*]])
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// RV64ZBC-NEXT: ret i64 [[TMP0]]
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//
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uint64_t clmul_64(uint64_t a, uint64_t b) {
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return __riscv_clmul_64(a, b);
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}
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// RV64ZBC-LABEL: @clmulh_64(
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// RV64ZBC-NEXT: entry:
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// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmulh.i64(i64 [[A:%.*]], i64 [[B:%.*]])
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// RV64ZBC-NEXT: ret i64 [[TMP0]]
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//
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uint64_t clmulh_64(uint64_t a, uint64_t b) {
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return __riscv_clmulh_64(a, b);
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}
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// RV64ZBC-LABEL: @clmulr_64(
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// RV64ZBC-NEXT: entry:
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// RV64ZBC-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.clmulr.i64(i64 [[A:%.*]], i64 [[B:%.*]])
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// RV64ZBC-NEXT: ret i64 [[TMP0]]
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//
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uint64_t clmulr_64(uint64_t a, uint64_t b) {
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return __riscv_clmulr_64(a, b);
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}
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#endif
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// RV32ZBC-LABEL: @clmul_32(
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// RV32ZBC-NEXT: entry:
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// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
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// RV32ZBC-NEXT: ret i32 [[TMP0]]
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//
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// RV64ZBC-LABEL: @clmul_32(
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// RV64ZBC-NEXT: entry:
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// RV64ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.clmul.i32(i32 [[A:%.*]], i32 [[B:%.*]])
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// RV64ZBC-NEXT: ret i32 [[TMP0]]
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//
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uint32_t clmul_32(uint32_t a, uint32_t b) {
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return __riscv_clmul_32(a, b);
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}
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#if __riscv_xlen == 32
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// RV32ZBC-LABEL: @clmulh_32(
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// RV32ZBC-NEXT: entry:
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// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulh.i32(i32 [[A:%.*]], i32 [[B:%.*]])
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// RV32ZBC-NEXT: ret i32 [[TMP0]]
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//
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uint32_t clmulh_32(uint32_t a, uint32_t b) {
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return __riscv_clmulh_32(a, b);
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}
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// RV32ZBC-LABEL: @clmulr_32(
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// RV32ZBC-NEXT: entry:
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// RV32ZBC-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.clmulr.i32(i32 [[A:%.*]], i32 [[B:%.*]])
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// RV32ZBC-NEXT: ret i32 [[TMP0]]
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//
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uint32_t clmulr_32(uint32_t a, uint32_t b) {
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return __riscv_clmulr_32(a, b);
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}
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#endif
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