derek.holloway
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39 lines
1.3 KiB
C
39 lines
1.3 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple riscv32 -target-feature +zksh -emit-llvm %s -o - \
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// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
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// RUN: | FileCheck %s -check-prefix=RV32ZKSH
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// RUN: %clang_cc1 -triple riscv64 -target-feature +zksh -emit-llvm %s -o - \
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// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
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// RUN: | FileCheck %s -check-prefix=RV64ZKSH
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#include <riscv_crypto.h>
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// RV32ZKSH-LABEL: @sm3p0(
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// RV32ZKSH-NEXT: entry:
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// RV32ZKSH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[RS1:%.*]])
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// RV32ZKSH-NEXT: ret i32 [[TMP0]]
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//
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// RV64ZKSH-LABEL: @sm3p0(
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// RV64ZKSH-NEXT: entry:
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// RV64ZKSH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sm3p0(i32 [[RS1:%.*]])
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// RV64ZKSH-NEXT: ret i32 [[TMP0]]
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//
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uint32_t sm3p0(uint32_t rs1) {
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return __riscv_sm3p0(rs1);
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}
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// RV32ZKSH-LABEL: @sm3p1(
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// RV32ZKSH-NEXT: entry:
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// RV32ZKSH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[RS1:%.*]])
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// RV32ZKSH-NEXT: ret i32 [[TMP0]]
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//
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// RV64ZKSH-LABEL: @sm3p1(
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// RV64ZKSH-NEXT: entry:
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// RV64ZKSH-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.sm3p1(i32 [[RS1:%.*]])
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// RV64ZKSH-NEXT: ret i32 [[TMP0]]
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//
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uint32_t sm3p1(uint32_t rs1) {
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return __riscv_sm3p1(rs1);
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}
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