derek.holloway
7502bf64a4
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60 lines
2.2 KiB
C
60 lines
2.2 KiB
C
// REQUIRES: aarch64-registered-target
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// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -S \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
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// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
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// RUN: %clang_cc1 -triple arm64-darwin -fms-compatibility -emit-llvm \
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// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
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// From winnt.h
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// op0=1 encodings, use with __sys
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#define ARM64_SYSINSTR(op0, op1, crn, crm, op2) \
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( ((op1 & 7) << 11) | \
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((crn & 15) << 7) | \
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((crm & 15) << 3) | \
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((op2 & 7) << 0) )
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//
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// Sampling of instructions
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//
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#define ARM64_DC_CGDSW_EL1 ARM64_SYSINSTR(1,0, 7,10,6) // Clean of Data and Allocation Tags by Set/Way
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#define ARM64_IC_IALLU_EL1 ARM64_SYSINSTR(1,0, 7, 5,0) // Instruction Cache Invalidate All to PoU
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#define ARM64_AT_S1E2W ARM64_SYSINSTR(1,4, 7, 8,1) // Translate Stage1, EL2, write
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#define ARM64_TLBI_VMALLE1 ARM64_SYSINSTR(1,0, 8, 7,0) // Invalidate stage 1 TLB [CP15_TLBIALL]
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#define ARM64_CFP_RCTX ARM64_SYSINSTR(1,3, 7, 3,4) // Control Flow Prediction Restriction by Context
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// From intrin.h
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unsigned int __sys(int, __int64);
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void check__sys(__int64 v) {
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__int64 ret;
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__sys(ARM64_DC_CGDSW_EL1, v);
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// CHECK-ASM: sys #0, c7, c10, #6, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 0, i32 7, i32 10, i32 6, i64 %[[VAR]])
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__sys(ARM64_IC_IALLU_EL1, v);
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// CHECK-ASM: sys #0, c7, c5, #0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 0, i32 7, i32 5, i32 0, i64 %[[VAR]])
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__sys(ARM64_AT_S1E2W, v);
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// CHECK-ASM: at s1e2w, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 4, i32 7, i32 8, i32 1, i64 %[[VAR]])
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__sys(ARM64_TLBI_VMALLE1, v);
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// CHECK-ASM: sys #0, c8, c7, #0, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 0, i32 8, i32 7, i32 0, i64 %[[VAR]])
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__sys(ARM64_CFP_RCTX, v);
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// CHECK-ASM: sys #3, c7, c3, #4, x8
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// CHECK-IR: %[[VAR:.*]] = load i64,
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// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 3, i32 7, i32 3, i32 4, i64 %[[VAR]])
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}
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