derek.holloway
7502bf64a4
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236 lines
14 KiB
Plaintext
236 lines
14 KiB
Plaintext
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
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// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu tonga -emit-llvm -fcuda-is-device -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm -fcuda-is-device -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx1010 -emit-llvm -fcuda-is-device -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx1012 -emit-llvm -fcuda-is-device -o - %s | FileCheck %s
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#define __device__ __attribute__((device))
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// CHECK-LABEL: define dso_local void @_Z18test_div_fixup_f16PDF16_DF16_DF16_DF16_(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]], half noundef [[B:%.*]], half noundef [[C:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[C_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr
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// CHECK-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: store half [[B]], ptr [[B_ADDR_ASCAST]], align 2
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// CHECK-NEXT: store half [[C]], ptr [[C_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[B_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[C_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP3:%.*]] = call contract half @llvm.amdgcn.div.fixup.f16(half [[TMP0]], half [[TMP1]], half [[TMP2]])
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// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[TMP3]], ptr [[TMP4]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_div_fixup_f16(_Float16 *out, _Float16 a, _Float16 b, _Float16 c) {
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*out = __builtin_amdgcn_div_fixuph(a, b, c);
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}
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// CHECK-LABEL: define dso_local void @_Z12test_rcp_f16PDF16_DF16_(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = call contract half @llvm.amdgcn.rcp.f16(half [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[TMP1]], ptr [[TMP2]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_rcp_f16(_Float16 *out, _Float16 a) {
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*out = __builtin_amdgcn_rcph(a);
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}
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// CHECK-LABEL: define dso_local void @_Z13test_sqrt_f16PDF16_DF16_(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = call contract half @llvm.amdgcn.sqrt.f16(half [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[TMP1]], ptr [[TMP2]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_sqrt_f16(_Float16 *out, _Float16 a) {
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*out = __builtin_amdgcn_sqrth(a);
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}
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// CHECK-LABEL: define dso_local void @_Z12test_rsq_f16PDF16_DF16_(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = call contract half @llvm.amdgcn.rsq.f16(half [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[TMP1]], ptr [[TMP2]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_rsq_f16(_Float16 *out, _Float16 a) {
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*out = __builtin_amdgcn_rsqh(a);
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}
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// CHECK-LABEL: define dso_local void @_Z12test_sin_f16PDF16_DF16_(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = call contract half @llvm.amdgcn.sin.f16(half [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[TMP1]], ptr [[TMP2]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_sin_f16(_Float16 *out, _Float16 a) {
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*out = __builtin_amdgcn_sinh(a);
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}
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// CHECK-LABEL: define dso_local void @_Z12test_cos_f16PDF16_DF16_(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = call contract half @llvm.amdgcn.cos.f16(half [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[TMP1]], ptr [[TMP2]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_cos_f16(_Float16 *out, _Float16 a) {
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*out = __builtin_amdgcn_cosh(a);
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}
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// CHECK-LABEL: define dso_local void @_Z14test_ldexp_f16PDF16_DF16_i(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR_ASCAST]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR_ASCAST]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: [[TMP3:%.*]] = call contract half @llvm.ldexp.f16.i16(half [[TMP0]], i16 [[TMP2]])
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// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[TMP3]], ptr [[TMP4]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_ldexp_f16(_Float16 *out, _Float16 a, int b) {
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*out = __builtin_amdgcn_ldexph(a, b);
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}
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// CHECK-LABEL: define dso_local void @_Z19test_frexp_mant_f16PDF16_DF16_(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = call contract half @llvm.amdgcn.frexp.mant.f16(half [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[TMP1]], ptr [[TMP2]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_frexp_mant_f16(_Float16 *out, _Float16 a) {
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*out = __builtin_amdgcn_frexp_manth(a);
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}
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// CHECK-LABEL: define dso_local void @_Z18test_frexp_exp_f16PsDF16_(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store i16 [[TMP1]], ptr [[TMP2]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_frexp_exp_f16(short *out, _Float16 a) {
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*out = __builtin_amdgcn_frexp_exph(a);
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}
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// CHECK-LABEL: define dso_local void @_Z14test_fract_f16PDF16_DF16_(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = call contract half @llvm.amdgcn.fract.f16(half [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[TMP1]], ptr [[TMP2]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_fract_f16(_Float16 *out, _Float16 a) {
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*out = __builtin_amdgcn_fracth(a);
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}
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// CHECK-LABEL: define dso_local void @_Z14test_class_f16PDF16_DF16_i(
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// CHECK-SAME: ptr noundef [[OUT:%.*]], half noundef [[A:%.*]], i32 noundef [[B:%.*]]) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca half, align 2, addrspace(5)
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr
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// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr
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// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr
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// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[A]], ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: store i32 [[B]], ptr [[B_ADDR_ASCAST]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A_ADDR_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR_ASCAST]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.amdgcn.class.f16(half [[TMP0]], i32 [[TMP1]])
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// CHECK-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP2]] to half
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// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8
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// CHECK-NEXT: store half [[CONV]], ptr [[TMP3]], align 2
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// CHECK-NEXT: ret void
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//
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__device__ void test_class_f16(_Float16 *out, _Float16 a, int b) {
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*out = __builtin_amdgcn_classh(a, b);
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}
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