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48 lines
1.4 KiB
Plaintext
48 lines
1.4 KiB
Plaintext
// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx906 -x hip -fcuda-is-device -emit-llvm %s \
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// RUN: -o - | FileCheck %s
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constexpr static int OpCtrl()
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{
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return 15 + 1;
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}
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constexpr static int RowMask()
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{
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return 3 + 1;
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}
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constexpr static int BankMask()
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{
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return 2 + 1;
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}
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constexpr static bool BountCtrl()
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{
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return true & false;
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}
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// CHECK: call i32 @llvm.amdgcn.update.dpp.i32(i32 %0, i32 %1, i32 16, i32 0, i32 0, i1 false)
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__attribute__((global)) void test_update_dpp_const_fold_imm_operand_2(int* out, int a, int b)
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{
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*out = __builtin_amdgcn_update_dpp(a, b, OpCtrl(), 0, 0, false);
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}
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// CHECK: call i32 @llvm.amdgcn.update.dpp.i32(i32 %0, i32 %1, i32 0, i32 4, i32 0, i1 false)
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__attribute__((global)) void test_update_dpp_const_fold_imm_operand_3(int* out, int a, int b)
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{
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*out = __builtin_amdgcn_update_dpp(a, b, 0, RowMask(), 0, false);
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}
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// CHECK: call i32 @llvm.amdgcn.update.dpp.i32(i32 %0, i32 %1, i32 0, i32 0, i32 3, i1 false)
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__attribute__((global)) void test_update_dpp_const_fold_imm_operand_4(int* out, int a, int b)
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{
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*out = __builtin_amdgcn_update_dpp(a, b, 0, 0, BankMask(), false);
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}
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// CHECK: call i32 @llvm.amdgcn.update.dpp.i32(i32 %0, i32 %1, i32 0, i32 0, i32 0, i1 false)
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__attribute__((global)) void test_update_dpp_const_fold_imm_operand_5(int* out, int a, int b)
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{
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*out = __builtin_amdgcn_update_dpp(a, b, 0, 0, 0, BountCtrl());
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}
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