derek.holloway
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79 lines
3.7 KiB
Common Lisp
79 lines
3.7 KiB
Common Lisp
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -target-cpu gfx1250 -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-GFX1250
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typedef int v4i __attribute__((ext_vector_type(4)));
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typedef int v8i __attribute__((ext_vector_type(8)));
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typedef unsigned int v4u __attribute__((ext_vector_type(4)));
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static v4i v4i_zeros = (v4i){0,0,0,0};
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static v8i v8i_zeros = (v8i){0,0,0,0,0,0,0,0};
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// CHECK-GFX1250-LABEL: @test_amdgcn_tensor_load_to_lds_d4(
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// CHECK-GFX1250-NEXT: entry:
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// CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> [[SG2:%.*]], <4 x i32> [[SG3:%.*]], <8 x i32> zeroinitializer, i32 0)
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// CHECK-GFX1250-NEXT: ret void
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//
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void test_amdgcn_tensor_load_to_lds_d4(v4u sg0, v8i sg1, v4i sg2, v4i sg3)
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{
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__builtin_amdgcn_tensor_load_to_lds(sg0, sg1, sg2, sg3, v8i_zeros, 0);
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}
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// CHECK-GFX1250-LABEL: @test_amdgcn_tensor_load_to_lds_d2(
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// CHECK-GFX1250-NEXT: entry:
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// CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 27)
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// CHECK-GFX1250-NEXT: ret void
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//
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void test_amdgcn_tensor_load_to_lds_d2(v4u sg0, v8i sg1)
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{
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__builtin_amdgcn_tensor_load_to_lds(sg0, sg1, v4i_zeros, v4i_zeros, v8i_zeros, 27);
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}
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// CHECK-GFX1250-LABEL: @test_amdgcn_tensor_store_from_lds_d4(
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// CHECK-GFX1250-NEXT: entry:
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// CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> [[SG2:%.*]], <4 x i32> [[SG3:%.*]], <8 x i32> zeroinitializer, i32 22)
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// CHECK-GFX1250-NEXT: ret void
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//
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void test_amdgcn_tensor_store_from_lds_d4(v4u sg0, v8i sg1, v4i sg2, v4i sg3)
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{
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__builtin_amdgcn_tensor_store_from_lds(sg0, sg1, sg2, sg3, v8i_zeros, 22);
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}
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// CHECK-GFX1250-LABEL: @test_amdgcn_tensor_store_from_lds_d2(
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// CHECK-GFX1250-NEXT: entry:
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// CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
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// CHECK-GFX1250-NEXT: ret void
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//
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void test_amdgcn_tensor_store_from_lds_d2(v4u sg0, v8i sg1)
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{
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__builtin_amdgcn_tensor_store_from_lds(sg0, sg1, v4i_zeros, v4i_zeros, v8i_zeros, 0);
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}
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//=======================================================================
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// It is fine to pass 5 arguments as tensor descriptor, but the fifth one
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// will be ignored by llvm CodeGen for gfx1250, which only supports D# up
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// to 4 groups.
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//========================================================================
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// CHECK-GFX1250-LABEL: @test_amdgcn_tensor_load_to_lds_d5(
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// CHECK-GFX1250-NEXT: entry:
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// CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> [[SG2:%.*]], <4 x i32> [[SG3:%.*]], <8 x i32> [[SG4:%.*]], i32 0)
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// CHECK-GFX1250-NEXT: ret void
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//
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void test_amdgcn_tensor_load_to_lds_d5(v4u sg0, v8i sg1, v4i sg2, v4i sg3, v8i sg4)
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{
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__builtin_amdgcn_tensor_load_to_lds(sg0, sg1, sg2, sg3, sg4, 0);
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}
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// CHECK-GFX1250-LABEL: @test_amdgcn_tensor_store_from_lds_d5(
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// CHECK-GFX1250-NEXT: entry:
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// CHECK-GFX1250-NEXT: tail call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> [[SG0:%.*]], <8 x i32> [[SG1:%.*]], <4 x i32> [[SG2:%.*]], <4 x i32> [[SG3:%.*]], <8 x i32> [[SG4:%.*]], i32 0)
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// CHECK-GFX1250-NEXT: ret void
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//
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void test_amdgcn_tensor_store_from_lds_d5(v4u sg0, v8i sg1, v4i sg2, v4i sg3, v8i sg4)
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{
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__builtin_amdgcn_tensor_store_from_lds(sg0, sg1, sg2, sg3, sg4, 0);
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}
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