derek.holloway
7502bf64a4
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628 lines
50 KiB
Common Lisp
628 lines
50 KiB
Common Lisp
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
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// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -mcode-object-version=5 -target-cpu tahiti -emit-llvm -o - %s | FileCheck -check-prefixes=NONUNIFORM-V5 %s
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// RUN: %clang_cc1 -cl-std=CL2.0 -cl-uniform-work-group-size -triple amdgcn-unknown-unknown -mcode-object-version=5 -target-cpu tahiti -emit-llvm -o - %s | FileCheck -check-prefixes=UNIFORM-V5 %s
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// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -mcode-object-version=4 -target-cpu tahiti -emit-llvm -o - %s | FileCheck -check-prefixes=NONUNIFORM-V4 %s
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// RUN: %clang_cc1 -cl-std=CL2.0 -cl-uniform-work-group-size -triple amdgcn-unknown-unknown -mcode-object-version=4 -target-cpu tahiti -emit-llvm -o - %s | FileCheck -check-prefixes=UNIFORM-V4 %s
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// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -mcode-object-version=none -emit-llvm -o - %s | FileCheck -check-prefixes=NONUNIFORM-UNKNOWN %s
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// RUN: %clang_cc1 -cl-std=CL2.0 -cl-uniform-work-group-size -triple amdgcn-unknown-unknown -mcode-object-version=none -emit-llvm -o - %s | FileCheck -check-prefixes=UNIFORM-UNKNOWN %s
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// NONUNIFORM-V5-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_x(
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// NONUNIFORM-V5-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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// NONUNIFORM-V5-NEXT: [[ENTRY:.*:]]
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// NONUNIFORM-V5-NEXT: [[TMP0:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// NONUNIFORM-V5-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) [[TMP0]], align 8, !invariant.load [[META7:![0-9]+]], !noundef [[META7]]
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// NONUNIFORM-V5-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.x()
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// NONUNIFORM-V5-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], [[TMP1]]
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// NONUNIFORM-V5-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i64 12, i64 18
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// NONUNIFORM-V5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 [[TMP4]]
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// NONUNIFORM-V5-NEXT: [[TMP6:%.*]] = load i16, ptr addrspace(4) [[TMP5]], align 2, !range [[RNG8:![0-9]+]], !invariant.load [[META7]], !noundef [[META7]]
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// NONUNIFORM-V5-NEXT: [[TMP7:%.*]] = zext nneg i16 [[TMP6]] to i32
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// NONUNIFORM-V5-NEXT: ret i32 [[TMP7]]
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//
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// UNIFORM-V5-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_x(
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// UNIFORM-V5-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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// UNIFORM-V5-NEXT: [[ENTRY:.*:]]
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// UNIFORM-V5-NEXT: [[TMP0:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// UNIFORM-V5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 12
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// UNIFORM-V5-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG7:![0-9]+]], !invariant.load [[META8:![0-9]+]], !noundef [[META8]]
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// UNIFORM-V5-NEXT: [[TMP3:%.*]] = zext nneg i16 [[TMP2]] to i32
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// UNIFORM-V5-NEXT: ret i32 [[TMP3]]
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//
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// NONUNIFORM-V4-LABEL: define dso_local range(i32 0, 1025) i32 @test_get_workgroup_size_x(
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// NONUNIFORM-V4-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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// NONUNIFORM-V4-NEXT: [[ENTRY:.*:]]
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// NONUNIFORM-V4-NEXT: [[TMP0:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// NONUNIFORM-V4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 4
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// NONUNIFORM-V4-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG7:![0-9]+]], !invariant.load [[META8:![0-9]+]], !noundef [[META8]]
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// NONUNIFORM-V4-NEXT: [[TMP3:%.*]] = zext nneg i16 [[TMP2]] to i32
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// NONUNIFORM-V4-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.x()
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// NONUNIFORM-V4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 12
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// NONUNIFORM-V4-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(4) [[TMP5]], align 4, !range [[RNG9:![0-9]+]], !invariant.load [[META8]]
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// NONUNIFORM-V4-NEXT: [[TMP7:%.*]] = mul i32 [[TMP4]], [[TMP3]]
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// NONUNIFORM-V4-NEXT: [[TMP8:%.*]] = sub i32 [[TMP6]], [[TMP7]]
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// NONUNIFORM-V4-NEXT: [[TMP9:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP8]], i32 [[TMP3]])
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// NONUNIFORM-V4-NEXT: ret i32 [[TMP9]]
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//
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// UNIFORM-V4-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_x(
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// UNIFORM-V4-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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// UNIFORM-V4-NEXT: [[ENTRY:.*:]]
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// UNIFORM-V4-NEXT: [[TMP0:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// UNIFORM-V4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 4
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// UNIFORM-V4-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG7:![0-9]+]], !invariant.load [[META8:![0-9]+]], !noundef [[META8]]
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// UNIFORM-V4-NEXT: [[TMP3:%.*]] = zext nneg i16 [[TMP2]] to i32
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// UNIFORM-V4-NEXT: ret i32 [[TMP3]]
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//
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// NONUNIFORM-UNKNOWN-LABEL: define dso_local range(i32 0, 1025) i32 @test_get_workgroup_size_x(
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// NONUNIFORM-UNKNOWN-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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// NONUNIFORM-UNKNOWN-NEXT: [[ENTRY:.*:]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 499
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP2:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 8, !invariant.load [[META6:![0-9]+]], !noundef [[META6]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.x()
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], [[TMP3]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i64 12, i64 18
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP2]], i64 [[TMP6]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP8:%.*]] = load i16, ptr addrspace(4) [[TMP7]], align 2, !range [[RNG7:![0-9]+]], !invariant.load [[META6]], !noundef [[META6]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP9:%.*]] = zext nneg i16 [[TMP8]] to i32
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP10:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP10]], i64 4
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP12:%.*]] = load i16, ptr addrspace(4) [[TMP11]], align 4, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP13:%.*]] = zext nneg i16 [[TMP12]] to i32
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP10]], i64 12
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(4) [[TMP14]], align 4, !range [[RNG8:![0-9]+]], !invariant.load [[META6]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP16:%.*]] = mul i32 [[TMP4]], [[TMP13]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP17:%.*]] = sub i32 [[TMP15]], [[TMP16]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP18:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP17]], i32 [[TMP13]])
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP19:%.*]] = select i1 [[TMP1]], i32 [[TMP9]], i32 [[TMP18]]
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// NONUNIFORM-UNKNOWN-NEXT: ret i32 [[TMP19]]
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//
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// UNIFORM-UNKNOWN-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_x(
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// UNIFORM-UNKNOWN-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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// UNIFORM-UNKNOWN-NEXT: [[ENTRY:.*:]]
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// UNIFORM-UNKNOWN-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
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// UNIFORM-UNKNOWN-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 499
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// UNIFORM-UNKNOWN-NEXT: [[TMP2:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// UNIFORM-UNKNOWN-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP2]], i64 12
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// UNIFORM-UNKNOWN-NEXT: [[TMP4:%.*]] = load i16, ptr addrspace(4) [[TMP3]], align 4, !range [[RNG6:![0-9]+]], !invariant.load [[META7:![0-9]+]], !noundef [[META7]]
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// UNIFORM-UNKNOWN-NEXT: [[TMP5:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// UNIFORM-UNKNOWN-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP5]], i64 4
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// UNIFORM-UNKNOWN-NEXT: [[TMP7:%.*]] = load i16, ptr addrspace(4) [[TMP6]], align 4, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
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// UNIFORM-UNKNOWN-NEXT: [[DOTV:%.*]] = select i1 [[TMP1]], i16 [[TMP4]], i16 [[TMP7]]
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// UNIFORM-UNKNOWN-NEXT: [[TMP8:%.*]] = zext nneg i16 [[DOTV]] to i32
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// UNIFORM-UNKNOWN-NEXT: ret i32 [[TMP8]]
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//
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unsigned int test_get_workgroup_size_x()
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{
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return __builtin_amdgcn_workgroup_size_x();
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}
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// NONUNIFORM-V5-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_y(
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// NONUNIFORM-V5-SAME: ) local_unnamed_addr #[[ATTR2:[0-9]+]] {
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// NONUNIFORM-V5-NEXT: [[ENTRY:.*:]]
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// NONUNIFORM-V5-NEXT: [[TMP0:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// NONUNIFORM-V5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 4
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// NONUNIFORM-V5-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[TMP1]], align 4, !invariant.load [[META7]], !noundef [[META7]]
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// NONUNIFORM-V5-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.y()
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// NONUNIFORM-V5-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], [[TMP2]]
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// NONUNIFORM-V5-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 14, i64 20
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// NONUNIFORM-V5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 [[TMP5]]
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// NONUNIFORM-V5-NEXT: [[TMP7:%.*]] = load i16, ptr addrspace(4) [[TMP6]], align 2, !range [[RNG8]], !invariant.load [[META7]], !noundef [[META7]]
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// NONUNIFORM-V5-NEXT: [[TMP8:%.*]] = zext nneg i16 [[TMP7]] to i32
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// NONUNIFORM-V5-NEXT: ret i32 [[TMP8]]
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//
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// UNIFORM-V5-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_y(
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// UNIFORM-V5-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// UNIFORM-V5-NEXT: [[ENTRY:.*:]]
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// UNIFORM-V5-NEXT: [[TMP0:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// UNIFORM-V5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 14
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// UNIFORM-V5-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 2, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
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// UNIFORM-V5-NEXT: [[TMP3:%.*]] = zext nneg i16 [[TMP2]] to i32
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// UNIFORM-V5-NEXT: ret i32 [[TMP3]]
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//
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// NONUNIFORM-V4-LABEL: define dso_local range(i32 0, 1025) i32 @test_get_workgroup_size_y(
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// NONUNIFORM-V4-SAME: ) local_unnamed_addr #[[ATTR2:[0-9]+]] {
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// NONUNIFORM-V4-NEXT: [[ENTRY:.*:]]
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// NONUNIFORM-V4-NEXT: [[TMP0:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// NONUNIFORM-V4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 6
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// NONUNIFORM-V4-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 2, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
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// NONUNIFORM-V4-NEXT: [[TMP3:%.*]] = zext nneg i16 [[TMP2]] to i32
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// NONUNIFORM-V4-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.y()
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// NONUNIFORM-V4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 16
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// NONUNIFORM-V4-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(4) [[TMP5]], align 4, !range [[RNG9]], !invariant.load [[META8]]
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// NONUNIFORM-V4-NEXT: [[TMP7:%.*]] = mul i32 [[TMP4]], [[TMP3]]
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// NONUNIFORM-V4-NEXT: [[TMP8:%.*]] = sub i32 [[TMP6]], [[TMP7]]
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// NONUNIFORM-V4-NEXT: [[TMP9:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP8]], i32 [[TMP3]])
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// NONUNIFORM-V4-NEXT: ret i32 [[TMP9]]
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//
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// UNIFORM-V4-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_y(
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// UNIFORM-V4-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// UNIFORM-V4-NEXT: [[ENTRY:.*:]]
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// UNIFORM-V4-NEXT: [[TMP0:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// UNIFORM-V4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 6
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// UNIFORM-V4-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 2, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
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// UNIFORM-V4-NEXT: [[TMP3:%.*]] = zext nneg i16 [[TMP2]] to i32
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// UNIFORM-V4-NEXT: ret i32 [[TMP3]]
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//
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// NONUNIFORM-UNKNOWN-LABEL: define dso_local range(i32 0, 1025) i32 @test_get_workgroup_size_y(
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// NONUNIFORM-UNKNOWN-SAME: ) local_unnamed_addr #[[ATTR2:[0-9]+]] {
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// NONUNIFORM-UNKNOWN-NEXT: [[ENTRY:.*:]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 499
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP2:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP2]], i64 4
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(4) [[TMP3]], align 4, !invariant.load [[META6]], !noundef [[META6]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.y()
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], [[TMP4]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 14, i64 20
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP2]], i64 [[TMP7]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP9:%.*]] = load i16, ptr addrspace(4) [[TMP8]], align 2, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP10:%.*]] = zext nneg i16 [[TMP9]] to i32
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP11:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP11]], i64 6
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP13:%.*]] = load i16, ptr addrspace(4) [[TMP12]], align 2, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP14:%.*]] = zext nneg i16 [[TMP13]] to i32
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP11]], i64 16
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// NONUNIFORM-UNKNOWN-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(4) [[TMP15]], align 4, !range [[RNG8]], !invariant.load [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP17:%.*]] = mul i32 [[TMP5]], [[TMP14]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP18:%.*]] = sub i32 [[TMP16]], [[TMP17]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP19:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP18]], i32 [[TMP14]])
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP20:%.*]] = select i1 [[TMP1]], i32 [[TMP10]], i32 [[TMP19]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: ret i32 [[TMP20]]
|
|
//
|
|
// UNIFORM-UNKNOWN-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_y(
|
|
// UNIFORM-UNKNOWN-SAME: ) local_unnamed_addr #[[ATTR0]] {
|
|
// UNIFORM-UNKNOWN-NEXT: [[ENTRY:.*:]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 499
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP2:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP2]], i64 14
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP4:%.*]] = load i16, ptr addrspace(4) [[TMP3]], align 2, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP5:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP5]], i64 6
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP7:%.*]] = load i16, ptr addrspace(4) [[TMP6]], align 2, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[DOTV:%.*]] = select i1 [[TMP1]], i16 [[TMP4]], i16 [[TMP7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP8:%.*]] = zext nneg i16 [[DOTV]] to i32
|
|
// UNIFORM-UNKNOWN-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
unsigned int test_get_workgroup_size_y()
|
|
{
|
|
return __builtin_amdgcn_workgroup_size_y();
|
|
}
|
|
|
|
// NONUNIFORM-V5-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_z(
|
|
// NONUNIFORM-V5-SAME: ) local_unnamed_addr #[[ATTR3:[0-9]+]] {
|
|
// NONUNIFORM-V5-NEXT: [[ENTRY:.*:]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP0:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// NONUNIFORM-V5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 8
|
|
// NONUNIFORM-V5-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[TMP1]], align 8, !invariant.load [[META7]], !noundef [[META7]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.z()
|
|
// NONUNIFORM-V5-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], [[TMP2]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 16, i64 22
|
|
// NONUNIFORM-V5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 [[TMP5]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP7:%.*]] = load i16, ptr addrspace(4) [[TMP6]], align 2, !range [[RNG8]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP8:%.*]] = zext nneg i16 [[TMP7]] to i32
|
|
// NONUNIFORM-V5-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
// UNIFORM-V5-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_z(
|
|
// UNIFORM-V5-SAME: ) local_unnamed_addr #[[ATTR0]] {
|
|
// UNIFORM-V5-NEXT: [[ENTRY:.*:]]
|
|
// UNIFORM-V5-NEXT: [[TMP0:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// UNIFORM-V5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 16
|
|
// UNIFORM-V5-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 8, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// UNIFORM-V5-NEXT: [[TMP3:%.*]] = zext nneg i16 [[TMP2]] to i32
|
|
// UNIFORM-V5-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// NONUNIFORM-V4-LABEL: define dso_local range(i32 0, 1025) i32 @test_get_workgroup_size_z(
|
|
// NONUNIFORM-V4-SAME: ) local_unnamed_addr #[[ATTR3:[0-9]+]] {
|
|
// NONUNIFORM-V4-NEXT: [[ENTRY:.*:]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP0:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// NONUNIFORM-V4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 8
|
|
// NONUNIFORM-V4-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP3:%.*]] = zext nneg i16 [[TMP2]] to i32
|
|
// NONUNIFORM-V4-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.z()
|
|
// NONUNIFORM-V4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 20
|
|
// NONUNIFORM-V4-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(4) [[TMP5]], align 4, !range [[RNG9]], !invariant.load [[META8]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP7:%.*]] = mul i32 [[TMP4]], [[TMP3]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP8:%.*]] = sub i32 [[TMP6]], [[TMP7]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP9:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP8]], i32 [[TMP3]])
|
|
// NONUNIFORM-V4-NEXT: ret i32 [[TMP9]]
|
|
//
|
|
// UNIFORM-V4-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_z(
|
|
// UNIFORM-V4-SAME: ) local_unnamed_addr #[[ATTR0]] {
|
|
// UNIFORM-V4-NEXT: [[ENTRY:.*:]]
|
|
// UNIFORM-V4-NEXT: [[TMP0:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// UNIFORM-V4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 8
|
|
// UNIFORM-V4-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// UNIFORM-V4-NEXT: [[TMP3:%.*]] = zext nneg i16 [[TMP2]] to i32
|
|
// UNIFORM-V4-NEXT: ret i32 [[TMP3]]
|
|
//
|
|
// NONUNIFORM-UNKNOWN-LABEL: define dso_local range(i32 0, 1025) i32 @test_get_workgroup_size_z(
|
|
// NONUNIFORM-UNKNOWN-SAME: ) local_unnamed_addr #[[ATTR3:[0-9]+]] {
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[ENTRY:.*:]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 499
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP2:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP2]], i64 8
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(4) [[TMP3]], align 8, !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.z()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], [[TMP4]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i64 16, i64 22
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP2]], i64 [[TMP7]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP9:%.*]] = load i16, ptr addrspace(4) [[TMP8]], align 2, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP10:%.*]] = zext nneg i16 [[TMP9]] to i32
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP11:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP11]], i64 8
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP13:%.*]] = load i16, ptr addrspace(4) [[TMP12]], align 4, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP14:%.*]] = zext nneg i16 [[TMP13]] to i32
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP11]], i64 20
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(4) [[TMP15]], align 4, !range [[RNG8]], !invariant.load [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP17:%.*]] = mul i32 [[TMP5]], [[TMP14]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP18:%.*]] = sub i32 [[TMP16]], [[TMP17]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP19:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP18]], i32 [[TMP14]])
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP20:%.*]] = select i1 [[TMP1]], i32 [[TMP10]], i32 [[TMP19]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: ret i32 [[TMP20]]
|
|
//
|
|
// UNIFORM-UNKNOWN-LABEL: define dso_local range(i32 1, 1025) i32 @test_get_workgroup_size_z(
|
|
// UNIFORM-UNKNOWN-SAME: ) local_unnamed_addr #[[ATTR0]] {
|
|
// UNIFORM-UNKNOWN-NEXT: [[ENTRY:.*:]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 499
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP2:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP2]], i64 16
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP4:%.*]] = load i16, ptr addrspace(4) [[TMP3]], align 8, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP5:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP5]], i64 8
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP7:%.*]] = load i16, ptr addrspace(4) [[TMP6]], align 4, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[DOTV:%.*]] = select i1 [[TMP1]], i16 [[TMP4]], i16 [[TMP7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP8:%.*]] = zext nneg i16 [[DOTV]] to i32
|
|
// UNIFORM-UNKNOWN-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
unsigned int test_get_workgroup_size_z()
|
|
{
|
|
return __builtin_amdgcn_workgroup_size_z();
|
|
}
|
|
|
|
// NONUNIFORM-V5-LABEL: define dso_local void @test_get_workgroup_size(
|
|
// NONUNIFORM-V5-SAME: i32 noundef [[D:%.*]], ptr addrspace(1) noundef writeonly captures(none) initializes((0, 4)) [[OUT:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] {
|
|
// NONUNIFORM-V5-NEXT: [[ENTRY:.*]]:
|
|
// NONUNIFORM-V5-NEXT: switch i32 [[D]], label %[[SW_EPILOG:.*]] [
|
|
// NONUNIFORM-V5-NEXT: i32 0, label %[[SW_BB:.*]]
|
|
// NONUNIFORM-V5-NEXT: i32 1, label %[[SW_BB1:.*]]
|
|
// NONUNIFORM-V5-NEXT: i32 2, label %[[SW_BB2:.*]]
|
|
// NONUNIFORM-V5-NEXT: ]
|
|
// NONUNIFORM-V5: [[SW_BB]]:
|
|
// NONUNIFORM-V5-NEXT: [[TMP0:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// NONUNIFORM-V5-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) [[TMP0]], align 8, !invariant.load [[META7]], !noundef [[META7]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.x()
|
|
// NONUNIFORM-V5-NEXT: [[TMP3:%.*]] = icmp ult i32 [[TMP2]], [[TMP1]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i64 12, i64 18
|
|
// NONUNIFORM-V5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 [[TMP4]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP6:%.*]] = load i16, ptr addrspace(4) [[TMP5]], align 2, !range [[RNG8]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// NONUNIFORM-V5-NEXT: [[NARROW:%.*]] = add nuw nsw i16 [[TMP6]], 1
|
|
// NONUNIFORM-V5-NEXT: br label %[[SW_EPILOG]]
|
|
// NONUNIFORM-V5: [[SW_BB1]]:
|
|
// NONUNIFORM-V5-NEXT: [[TMP7:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// NONUNIFORM-V5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP7]], i64 4
|
|
// NONUNIFORM-V5-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(4) [[TMP8]], align 4, !invariant.load [[META7]], !noundef [[META7]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP10:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.y()
|
|
// NONUNIFORM-V5-NEXT: [[TMP11:%.*]] = icmp ult i32 [[TMP10]], [[TMP9]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i64 14, i64 20
|
|
// NONUNIFORM-V5-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP7]], i64 [[TMP12]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP14:%.*]] = load i16, ptr addrspace(4) [[TMP13]], align 2, !range [[RNG8]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// NONUNIFORM-V5-NEXT: br label %[[SW_EPILOG]]
|
|
// NONUNIFORM-V5: [[SW_BB2]]:
|
|
// NONUNIFORM-V5-NEXT: [[TMP15:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// NONUNIFORM-V5-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP15]], i64 8
|
|
// NONUNIFORM-V5-NEXT: [[TMP17:%.*]] = load i32, ptr addrspace(4) [[TMP16]], align 8, !invariant.load [[META7]], !noundef [[META7]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP18:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.z()
|
|
// NONUNIFORM-V5-NEXT: [[TMP19:%.*]] = icmp ult i32 [[TMP18]], [[TMP17]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i64 16, i64 22
|
|
// NONUNIFORM-V5-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP15]], i64 [[TMP20]]
|
|
// NONUNIFORM-V5-NEXT: [[TMP22:%.*]] = load i16, ptr addrspace(4) [[TMP21]], align 2, !range [[RNG8]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// NONUNIFORM-V5-NEXT: br label %[[SW_EPILOG]]
|
|
// NONUNIFORM-V5: [[SW_EPILOG]]:
|
|
// NONUNIFORM-V5-NEXT: [[DOTSINK_SHRUNK:%.*]] = phi i16 [ [[NARROW]], %[[SW_BB]] ], [ [[TMP22]], %[[SW_BB2]] ], [ [[TMP14]], %[[SW_BB1]] ], [ 0, %[[ENTRY]] ]
|
|
// NONUNIFORM-V5-NEXT: [[DOTSINK:%.*]] = zext i16 [[DOTSINK_SHRUNK]] to i32
|
|
// NONUNIFORM-V5-NEXT: store i32 [[DOTSINK]], ptr addrspace(1) [[OUT]], align 4, !tbaa [[INT_TBAA3:![0-9]+]]
|
|
// NONUNIFORM-V5-NEXT: ret void
|
|
//
|
|
// UNIFORM-V5-LABEL: define dso_local void @test_get_workgroup_size(
|
|
// UNIFORM-V5-SAME: i32 noundef [[D:%.*]], ptr addrspace(1) noundef writeonly captures(none) initializes((0, 4)) [[OUT:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] {
|
|
// UNIFORM-V5-NEXT: [[ENTRY:.*]]:
|
|
// UNIFORM-V5-NEXT: switch i32 [[D]], label %[[SW_EPILOG:.*]] [
|
|
// UNIFORM-V5-NEXT: i32 0, label %[[SW_BB:.*]]
|
|
// UNIFORM-V5-NEXT: i32 1, label %[[SW_BB1:.*]]
|
|
// UNIFORM-V5-NEXT: i32 2, label %[[SW_BB2:.*]]
|
|
// UNIFORM-V5-NEXT: ]
|
|
// UNIFORM-V5: [[SW_BB]]:
|
|
// UNIFORM-V5-NEXT: [[TMP0:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// UNIFORM-V5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 12
|
|
// UNIFORM-V5-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// UNIFORM-V5-NEXT: [[NARROW:%.*]] = add nuw nsw i16 [[TMP2]], 1
|
|
// UNIFORM-V5-NEXT: br label %[[SW_EPILOG]]
|
|
// UNIFORM-V5: [[SW_BB1]]:
|
|
// UNIFORM-V5-NEXT: [[TMP3:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// UNIFORM-V5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP3]], i64 14
|
|
// UNIFORM-V5-NEXT: [[TMP5:%.*]] = load i16, ptr addrspace(4) [[TMP4]], align 2, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// UNIFORM-V5-NEXT: br label %[[SW_EPILOG]]
|
|
// UNIFORM-V5: [[SW_BB2]]:
|
|
// UNIFORM-V5-NEXT: [[TMP6:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// UNIFORM-V5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP6]], i64 16
|
|
// UNIFORM-V5-NEXT: [[TMP8:%.*]] = load i16, ptr addrspace(4) [[TMP7]], align 8, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// UNIFORM-V5-NEXT: br label %[[SW_EPILOG]]
|
|
// UNIFORM-V5: [[SW_EPILOG]]:
|
|
// UNIFORM-V5-NEXT: [[DOTSINK_SHRUNK:%.*]] = phi i16 [ [[NARROW]], %[[SW_BB]] ], [ [[TMP8]], %[[SW_BB2]] ], [ [[TMP5]], %[[SW_BB1]] ], [ 0, %[[ENTRY]] ]
|
|
// UNIFORM-V5-NEXT: [[DOTSINK:%.*]] = zext i16 [[DOTSINK_SHRUNK]] to i32
|
|
// UNIFORM-V5-NEXT: store i32 [[DOTSINK]], ptr addrspace(1) [[OUT]], align 4, !tbaa [[INT_TBAA3:![0-9]+]]
|
|
// UNIFORM-V5-NEXT: ret void
|
|
//
|
|
// NONUNIFORM-V4-LABEL: define dso_local void @test_get_workgroup_size(
|
|
// NONUNIFORM-V4-SAME: i32 noundef [[D:%.*]], ptr addrspace(1) noundef writeonly captures(none) initializes((0, 4)) [[OUT:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] {
|
|
// NONUNIFORM-V4-NEXT: [[ENTRY:.*]]:
|
|
// NONUNIFORM-V4-NEXT: switch i32 [[D]], label %[[SW_EPILOG:.*]] [
|
|
// NONUNIFORM-V4-NEXT: i32 0, label %[[SW_BB:.*]]
|
|
// NONUNIFORM-V4-NEXT: i32 1, label %[[SW_BB1:.*]]
|
|
// NONUNIFORM-V4-NEXT: i32 2, label %[[SW_BB2:.*]]
|
|
// NONUNIFORM-V4-NEXT: ]
|
|
// NONUNIFORM-V4: [[SW_BB]]:
|
|
// NONUNIFORM-V4-NEXT: [[TMP0:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// NONUNIFORM-V4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 4
|
|
// NONUNIFORM-V4-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP3:%.*]] = zext nneg i16 [[TMP2]] to i32
|
|
// NONUNIFORM-V4-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.x()
|
|
// NONUNIFORM-V4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 12
|
|
// NONUNIFORM-V4-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(4) [[TMP5]], align 4, !range [[RNG9]], !invariant.load [[META8]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP7:%.*]] = mul i32 [[TMP4]], [[TMP3]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP8:%.*]] = sub i32 [[TMP6]], [[TMP7]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP9:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP8]], i32 [[TMP3]])
|
|
// NONUNIFORM-V4-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[TMP9]], 1
|
|
// NONUNIFORM-V4-NEXT: br label %[[SW_EPILOG]]
|
|
// NONUNIFORM-V4: [[SW_BB1]]:
|
|
// NONUNIFORM-V4-NEXT: [[TMP10:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// NONUNIFORM-V4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP10]], i64 6
|
|
// NONUNIFORM-V4-NEXT: [[TMP12:%.*]] = load i16, ptr addrspace(4) [[TMP11]], align 2, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP13:%.*]] = zext nneg i16 [[TMP12]] to i32
|
|
// NONUNIFORM-V4-NEXT: [[TMP14:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.y()
|
|
// NONUNIFORM-V4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP10]], i64 16
|
|
// NONUNIFORM-V4-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(4) [[TMP15]], align 4, !range [[RNG9]], !invariant.load [[META8]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP17:%.*]] = mul i32 [[TMP14]], [[TMP13]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP18:%.*]] = sub i32 [[TMP16]], [[TMP17]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP19:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP18]], i32 [[TMP13]])
|
|
// NONUNIFORM-V4-NEXT: br label %[[SW_EPILOG]]
|
|
// NONUNIFORM-V4: [[SW_BB2]]:
|
|
// NONUNIFORM-V4-NEXT: [[TMP20:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// NONUNIFORM-V4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP20]], i64 8
|
|
// NONUNIFORM-V4-NEXT: [[TMP22:%.*]] = load i16, ptr addrspace(4) [[TMP21]], align 4, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP23:%.*]] = zext nneg i16 [[TMP22]] to i32
|
|
// NONUNIFORM-V4-NEXT: [[TMP24:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.z()
|
|
// NONUNIFORM-V4-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP20]], i64 20
|
|
// NONUNIFORM-V4-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(4) [[TMP25]], align 4, !range [[RNG9]], !invariant.load [[META8]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP27:%.*]] = mul i32 [[TMP24]], [[TMP23]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP28:%.*]] = sub i32 [[TMP26]], [[TMP27]]
|
|
// NONUNIFORM-V4-NEXT: [[TMP29:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP28]], i32 [[TMP23]])
|
|
// NONUNIFORM-V4-NEXT: br label %[[SW_EPILOG]]
|
|
// NONUNIFORM-V4: [[SW_EPILOG]]:
|
|
// NONUNIFORM-V4-NEXT: [[DOTSINK:%.*]] = phi i32 [ [[ADD]], %[[SW_BB]] ], [ [[TMP29]], %[[SW_BB2]] ], [ [[TMP19]], %[[SW_BB1]] ], [ 0, %[[ENTRY]] ]
|
|
// NONUNIFORM-V4-NEXT: store i32 [[DOTSINK]], ptr addrspace(1) [[OUT]], align 4, !tbaa [[INT_TBAA3:![0-9]+]]
|
|
// NONUNIFORM-V4-NEXT: ret void
|
|
//
|
|
// UNIFORM-V4-LABEL: define dso_local void @test_get_workgroup_size(
|
|
// UNIFORM-V4-SAME: i32 noundef [[D:%.*]], ptr addrspace(1) noundef writeonly captures(none) initializes((0, 4)) [[OUT:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] {
|
|
// UNIFORM-V4-NEXT: [[ENTRY:.*]]:
|
|
// UNIFORM-V4-NEXT: switch i32 [[D]], label %[[SW_EPILOG:.*]] [
|
|
// UNIFORM-V4-NEXT: i32 0, label %[[SW_BB:.*]]
|
|
// UNIFORM-V4-NEXT: i32 1, label %[[SW_BB1:.*]]
|
|
// UNIFORM-V4-NEXT: i32 2, label %[[SW_BB2:.*]]
|
|
// UNIFORM-V4-NEXT: ]
|
|
// UNIFORM-V4: [[SW_BB]]:
|
|
// UNIFORM-V4-NEXT: [[TMP0:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// UNIFORM-V4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP0]], i64 4
|
|
// UNIFORM-V4-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// UNIFORM-V4-NEXT: [[NARROW:%.*]] = add nuw nsw i16 [[TMP2]], 1
|
|
// UNIFORM-V4-NEXT: br label %[[SW_EPILOG]]
|
|
// UNIFORM-V4: [[SW_BB1]]:
|
|
// UNIFORM-V4-NEXT: [[TMP3:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// UNIFORM-V4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP3]], i64 6
|
|
// UNIFORM-V4-NEXT: [[TMP5:%.*]] = load i16, ptr addrspace(4) [[TMP4]], align 2, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// UNIFORM-V4-NEXT: br label %[[SW_EPILOG]]
|
|
// UNIFORM-V4: [[SW_BB2]]:
|
|
// UNIFORM-V4-NEXT: [[TMP6:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// UNIFORM-V4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP6]], i64 8
|
|
// UNIFORM-V4-NEXT: [[TMP8:%.*]] = load i16, ptr addrspace(4) [[TMP7]], align 4, !range [[RNG7]], !invariant.load [[META8]], !noundef [[META8]]
|
|
// UNIFORM-V4-NEXT: br label %[[SW_EPILOG]]
|
|
// UNIFORM-V4: [[SW_EPILOG]]:
|
|
// UNIFORM-V4-NEXT: [[DOTSINK_SHRUNK:%.*]] = phi i16 [ [[NARROW]], %[[SW_BB]] ], [ [[TMP8]], %[[SW_BB2]] ], [ [[TMP5]], %[[SW_BB1]] ], [ 0, %[[ENTRY]] ]
|
|
// UNIFORM-V4-NEXT: [[DOTSINK:%.*]] = zext i16 [[DOTSINK_SHRUNK]] to i32
|
|
// UNIFORM-V4-NEXT: store i32 [[DOTSINK]], ptr addrspace(1) [[OUT]], align 4, !tbaa [[INT_TBAA3:![0-9]+]]
|
|
// UNIFORM-V4-NEXT: ret void
|
|
//
|
|
// NONUNIFORM-UNKNOWN-LABEL: define dso_local void @test_get_workgroup_size(
|
|
// NONUNIFORM-UNKNOWN-SAME: i32 noundef [[D:%.*]], ptr addrspace(1) noundef writeonly captures(none) initializes((0, 4)) [[OUT:%.*]]) local_unnamed_addr #[[ATTR4:[0-9]+]] {
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[ENTRY:.*]]:
|
|
// NONUNIFORM-UNKNOWN-NEXT: switch i32 [[D]], label %[[SW_EPILOG:.*]] [
|
|
// NONUNIFORM-UNKNOWN-NEXT: i32 0, label %[[SW_BB:.*]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: i32 1, label %[[SW_BB1:.*]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: i32 2, label %[[SW_BB2:.*]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: ]
|
|
// NONUNIFORM-UNKNOWN: [[SW_BB]]:
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 499
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP2:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 8, !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.x()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], [[TMP3]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i64 12, i64 18
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP2]], i64 [[TMP6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP8:%.*]] = load i16, ptr addrspace(4) [[TMP7]], align 2, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP9:%.*]] = zext nneg i16 [[TMP8]] to i32
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP10:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP10]], i64 4
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP12:%.*]] = load i16, ptr addrspace(4) [[TMP11]], align 4, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP13:%.*]] = zext nneg i16 [[TMP12]] to i32
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP10]], i64 12
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(4) [[TMP14]], align 4, !range [[RNG8]], !invariant.load [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP16:%.*]] = mul i32 [[TMP4]], [[TMP13]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP17:%.*]] = sub i32 [[TMP15]], [[TMP16]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP18:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP17]], i32 [[TMP13]])
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP19:%.*]] = select i1 [[TMP1]], i32 [[TMP9]], i32 [[TMP18]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[TMP19]], 1
|
|
// NONUNIFORM-UNKNOWN-NEXT: br label %[[SW_EPILOG]]
|
|
// NONUNIFORM-UNKNOWN: [[SW_BB1]]:
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP21:%.*]] = icmp sgt i32 [[TMP20]], 499
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP22:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP22]], i64 4
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP24:%.*]] = load i32, ptr addrspace(4) [[TMP23]], align 4, !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP25:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.y()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP24]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP27:%.*]] = select i1 [[TMP26]], i64 14, i64 20
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP22]], i64 [[TMP27]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP29:%.*]] = load i16, ptr addrspace(4) [[TMP28]], align 2, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP30:%.*]] = zext nneg i16 [[TMP29]] to i32
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP31:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP31]], i64 6
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP33:%.*]] = load i16, ptr addrspace(4) [[TMP32]], align 2, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP34:%.*]] = zext nneg i16 [[TMP33]] to i32
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP31]], i64 16
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP36:%.*]] = load i32, ptr addrspace(4) [[TMP35]], align 4, !range [[RNG8]], !invariant.load [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP37:%.*]] = mul i32 [[TMP25]], [[TMP34]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP38:%.*]] = sub i32 [[TMP36]], [[TMP37]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP39:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP38]], i32 [[TMP34]])
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP40:%.*]] = select i1 [[TMP21]], i32 [[TMP30]], i32 [[TMP39]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: br label %[[SW_EPILOG]]
|
|
// NONUNIFORM-UNKNOWN: [[SW_BB2]]:
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP41:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP42:%.*]] = icmp sgt i32 [[TMP41]], 499
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP43:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP44:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP43]], i64 8
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP45:%.*]] = load i32, ptr addrspace(4) [[TMP44]], align 8, !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP46:%.*]] = tail call i32 @llvm.amdgcn.workgroup.id.z()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP47:%.*]] = icmp ult i32 [[TMP46]], [[TMP45]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP48:%.*]] = select i1 [[TMP47]], i64 16, i64 22
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP43]], i64 [[TMP48]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP50:%.*]] = load i16, ptr addrspace(4) [[TMP49]], align 2, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP51:%.*]] = zext nneg i16 [[TMP50]] to i32
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP52:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP53:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP52]], i64 8
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP54:%.*]] = load i16, ptr addrspace(4) [[TMP53]], align 4, !range [[RNG7]], !invariant.load [[META6]], !noundef [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP55:%.*]] = zext nneg i16 [[TMP54]] to i32
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP52]], i64 20
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP57:%.*]] = load i32, ptr addrspace(4) [[TMP56]], align 4, !range [[RNG8]], !invariant.load [[META6]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP58:%.*]] = mul i32 [[TMP46]], [[TMP55]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP59:%.*]] = sub i32 [[TMP57]], [[TMP58]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP60:%.*]] = tail call i32 @llvm.umin.i32(i32 [[TMP59]], i32 [[TMP55]])
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[TMP61:%.*]] = select i1 [[TMP42]], i32 [[TMP51]], i32 [[TMP60]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: br label %[[SW_EPILOG]]
|
|
// NONUNIFORM-UNKNOWN: [[SW_EPILOG]]:
|
|
// NONUNIFORM-UNKNOWN-NEXT: [[DOTSINK:%.*]] = phi i32 [ [[ADD]], %[[SW_BB]] ], [ [[TMP61]], %[[SW_BB2]] ], [ [[TMP40]], %[[SW_BB1]] ], [ 0, %[[ENTRY]] ]
|
|
// NONUNIFORM-UNKNOWN-NEXT: store i32 [[DOTSINK]], ptr addrspace(1) [[OUT]], align 4, !tbaa [[INT_TBAA2:![0-9]+]]
|
|
// NONUNIFORM-UNKNOWN-NEXT: ret void
|
|
//
|
|
// UNIFORM-UNKNOWN-LABEL: define dso_local void @test_get_workgroup_size(
|
|
// UNIFORM-UNKNOWN-SAME: i32 noundef [[D:%.*]], ptr addrspace(1) noundef writeonly captures(none) initializes((0, 4)) [[OUT:%.*]]) local_unnamed_addr #[[ATTR2:[0-9]+]] {
|
|
// UNIFORM-UNKNOWN-NEXT: [[ENTRY:.*]]:
|
|
// UNIFORM-UNKNOWN-NEXT: switch i32 [[D]], label %[[SW_EPILOG:.*]] [
|
|
// UNIFORM-UNKNOWN-NEXT: i32 0, label %[[SW_BB:.*]]
|
|
// UNIFORM-UNKNOWN-NEXT: i32 1, label %[[SW_BB1:.*]]
|
|
// UNIFORM-UNKNOWN-NEXT: i32 2, label %[[SW_BB2:.*]]
|
|
// UNIFORM-UNKNOWN-NEXT: ]
|
|
// UNIFORM-UNKNOWN: [[SW_BB]]:
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 499
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP2:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP2]], i64 12
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP4:%.*]] = load i16, ptr addrspace(4) [[TMP3]], align 4, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP5:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP5]], i64 4
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP7:%.*]] = load i16, ptr addrspace(4) [[TMP6]], align 4, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[DOTV7:%.*]] = select i1 [[TMP1]], i16 [[TMP4]], i16 [[TMP7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[NARROW:%.*]] = add nuw nsw i16 [[DOTV7]], 1
|
|
// UNIFORM-UNKNOWN-NEXT: br label %[[SW_EPILOG]]
|
|
// UNIFORM-UNKNOWN: [[SW_BB1]]:
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP9:%.*]] = icmp sgt i32 [[TMP8]], 499
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP10:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP10]], i64 14
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP12:%.*]] = load i16, ptr addrspace(4) [[TMP11]], align 2, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
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|
// UNIFORM-UNKNOWN-NEXT: [[TMP13:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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|
// UNIFORM-UNKNOWN-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP13]], i64 6
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// UNIFORM-UNKNOWN-NEXT: [[TMP15:%.*]] = load i16, ptr addrspace(4) [[TMP14]], align 2, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
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|
// UNIFORM-UNKNOWN-NEXT: [[DOTV6:%.*]] = select i1 [[TMP9]], i16 [[TMP12]], i16 [[TMP15]]
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|
// UNIFORM-UNKNOWN-NEXT: br label %[[SW_EPILOG]]
|
|
// UNIFORM-UNKNOWN: [[SW_BB2]]:
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP17:%.*]] = icmp sgt i32 [[TMP16]], 499
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|
// UNIFORM-UNKNOWN-NEXT: [[TMP18:%.*]] = tail call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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|
// UNIFORM-UNKNOWN-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP18]], i64 16
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|
// UNIFORM-UNKNOWN-NEXT: [[TMP20:%.*]] = load i16, ptr addrspace(4) [[TMP19]], align 8, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP21:%.*]] = tail call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(4) [[TMP21]], i64 8
|
|
// UNIFORM-UNKNOWN-NEXT: [[TMP23:%.*]] = load i16, ptr addrspace(4) [[TMP22]], align 4, !range [[RNG6]], !invariant.load [[META7]], !noundef [[META7]]
|
|
// UNIFORM-UNKNOWN-NEXT: [[DOTV:%.*]] = select i1 [[TMP17]], i16 [[TMP20]], i16 [[TMP23]]
|
|
// UNIFORM-UNKNOWN-NEXT: br label %[[SW_EPILOG]]
|
|
// UNIFORM-UNKNOWN: [[SW_EPILOG]]:
|
|
// UNIFORM-UNKNOWN-NEXT: [[DOTSINK_SHRUNK:%.*]] = phi i16 [ [[NARROW]], %[[SW_BB]] ], [ [[DOTV]], %[[SW_BB2]] ], [ [[DOTV6]], %[[SW_BB1]] ], [ 0, %[[ENTRY]] ]
|
|
// UNIFORM-UNKNOWN-NEXT: [[DOTSINK:%.*]] = zext i16 [[DOTSINK_SHRUNK]] to i32
|
|
// UNIFORM-UNKNOWN-NEXT: store i32 [[DOTSINK]], ptr addrspace(1) [[OUT]], align 4, !tbaa [[INT_TBAA2:![0-9]+]]
|
|
// UNIFORM-UNKNOWN-NEXT: ret void
|
|
//
|
|
void test_get_workgroup_size(int d, global int *out)
|
|
{
|
|
switch (d) {
|
|
case 0: *out = __builtin_amdgcn_workgroup_size_x() + 1; break;
|
|
case 1: *out = __builtin_amdgcn_workgroup_size_y(); break;
|
|
case 2: *out = __builtin_amdgcn_workgroup_size_z(); break;
|
|
default: *out = 0;
|
|
}
|
|
}
|
|
|
|
|
|
//.
|
|
// NONUNIFORM-V5: [[INT_TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0}
|
|
// NONUNIFORM-V5: [[META4]] = !{!"int", [[META5:![0-9]+]], i64 0}
|
|
// NONUNIFORM-V5: [[META5]] = !{!"omnipotent char", [[META6:![0-9]+]], i64 0}
|
|
// NONUNIFORM-V5: [[META6]] = !{!"Simple C/C++ TBAA"}
|
|
// NONUNIFORM-V5: [[META7]] = !{}
|
|
// NONUNIFORM-V5: [[RNG8]] = !{i16 1, i16 1025}
|
|
//.
|
|
// UNIFORM-V5: [[INT_TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0}
|
|
// UNIFORM-V5: [[META4]] = !{!"int", [[META5:![0-9]+]], i64 0}
|
|
// UNIFORM-V5: [[META5]] = !{!"omnipotent char", [[META6:![0-9]+]], i64 0}
|
|
// UNIFORM-V5: [[META6]] = !{!"Simple C/C++ TBAA"}
|
|
// UNIFORM-V5: [[RNG7]] = !{i16 1, i16 1025}
|
|
// UNIFORM-V5: [[META8]] = !{}
|
|
//.
|
|
// NONUNIFORM-V4: [[INT_TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0}
|
|
// NONUNIFORM-V4: [[META4]] = !{!"int", [[META5:![0-9]+]], i64 0}
|
|
// NONUNIFORM-V4: [[META5]] = !{!"omnipotent char", [[META6:![0-9]+]], i64 0}
|
|
// NONUNIFORM-V4: [[META6]] = !{!"Simple C/C++ TBAA"}
|
|
// NONUNIFORM-V4: [[RNG7]] = !{i16 1, i16 1025}
|
|
// NONUNIFORM-V4: [[META8]] = !{}
|
|
// NONUNIFORM-V4: [[RNG9]] = !{i32 1, i32 0}
|
|
//.
|
|
// UNIFORM-V4: [[INT_TBAA3]] = !{[[META4:![0-9]+]], [[META4]], i64 0}
|
|
// UNIFORM-V4: [[META4]] = !{!"int", [[META5:![0-9]+]], i64 0}
|
|
// UNIFORM-V4: [[META5]] = !{!"omnipotent char", [[META6:![0-9]+]], i64 0}
|
|
// UNIFORM-V4: [[META6]] = !{!"Simple C/C++ TBAA"}
|
|
// UNIFORM-V4: [[RNG7]] = !{i16 1, i16 1025}
|
|
// UNIFORM-V4: [[META8]] = !{}
|
|
//.
|
|
// NONUNIFORM-UNKNOWN: [[INT_TBAA2]] = !{[[META3:![0-9]+]], [[META3]], i64 0}
|
|
// NONUNIFORM-UNKNOWN: [[META3]] = !{!"int", [[META4:![0-9]+]], i64 0}
|
|
// NONUNIFORM-UNKNOWN: [[META4]] = !{!"omnipotent char", [[META5:![0-9]+]], i64 0}
|
|
// NONUNIFORM-UNKNOWN: [[META5]] = !{!"Simple C/C++ TBAA"}
|
|
// NONUNIFORM-UNKNOWN: [[META6]] = !{}
|
|
// NONUNIFORM-UNKNOWN: [[RNG7]] = !{i16 1, i16 1025}
|
|
// NONUNIFORM-UNKNOWN: [[RNG8]] = !{i32 1, i32 0}
|
|
//.
|
|
// UNIFORM-UNKNOWN: [[INT_TBAA2]] = !{[[META3:![0-9]+]], [[META3]], i64 0}
|
|
// UNIFORM-UNKNOWN: [[META3]] = !{!"int", [[META4:![0-9]+]], i64 0}
|
|
// UNIFORM-UNKNOWN: [[META4]] = !{!"omnipotent char", [[META5:![0-9]+]], i64 0}
|
|
// UNIFORM-UNKNOWN: [[META5]] = !{!"Simple C/C++ TBAA"}
|
|
// UNIFORM-UNKNOWN: [[RNG6]] = !{i16 1, i16 1025}
|
|
// UNIFORM-UNKNOWN: [[META7]] = !{}
|
|
//.
|