derek.holloway
7502bf64a4
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72 lines
6.9 KiB
C
72 lines
6.9 KiB
C
// REQUIRES: riscv-registered-target
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// RUN: %clang --target=riscv64 -mcpu=sifive-x180 -menable-experimental-extensions --print-enabled-extensions | FileCheck %s
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// CHECK: Name Version Description
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// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
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// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
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// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
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// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
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// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
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// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
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// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
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// CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors)
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// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes)
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// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions)
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// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions)
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// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions)
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// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A)
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// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)
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// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
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// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations)
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// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
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// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
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// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints)
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// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint)
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// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters)
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// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations)
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// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
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// CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set Size of at Most 64 Bytes)
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// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
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// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
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// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set)
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// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point)
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// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts)
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// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point)
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// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal)
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// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
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// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions)
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// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
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// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations)
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// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
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// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
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// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
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// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency)
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// CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic bit-manipulation instructions)
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// CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)
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// CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)
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// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)
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// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)
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// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)
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// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16 Converts)
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// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add)
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// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point)
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// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)
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// CHECK-NEXT: zvkb 1.0 'Zvkb' (Vector Bit-manipulation used in Cryptography)
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// CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector Data-Independent Execution Latency)
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// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128)
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// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32)
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// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64)
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// CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction)
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// CHECK-NEXT: xsfvfbfexp16e 0.5 'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16)
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// CHECK-NEXT: xsfvfexp16e 0.5 'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision)
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// CHECK-NEXT: xsfvfexp32e 0.5 'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision)
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// CHECK-NEXT: xsfvfexpa 0.2 'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)
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// CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)
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// CHECK-EMPTY:
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// CHECK-NEXT: Experimental extensions
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// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
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// CHECK-NEXT: zvdot4a8i 0.1 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers)
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// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
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// CHECK-EMPTY:
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// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_ziccrse1p0_zicfilp1p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zvdot4a8i0p1_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfcease1p0_xsfvfbfexp16e0p5_xsfvfexp16e0p5_xsfvfexp32e0p5_xsfvfexpa0p2_xsifivecflushdlone1p0
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