derek.holloway
7502bf64a4
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32 lines
2.2 KiB
C
32 lines
2.2 KiB
C
// REQUIRES: arm-registered-target
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// RUN: %clang --target=arm-linux-gnu --print-supported-extensions | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
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// CHECK: All available -march extensions for ARM
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// CHECK-EMPTY:
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// CHECK-NEXT: Name Description
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// CHECK-NEXT: crc Enable support for CRC instructions
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// CHECK-NEXT: crypto Enable support for Cryptography extensions
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// CHECK-NEXT: sha2 Enable SHA1 and SHA256 support
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// CHECK-NEXT: aes Enable AES support
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// CHECK-NEXT: dotprod Enable support for dot product instructions
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// CHECK-NEXT: dsp Supports DSP instructions in ARM and/or Thumb2
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// CHECK-NEXT: mve Support M-Class Vector Extension with integer ops
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// CHECK-NEXT: mve.fp Support M-Class Vector Extension with integer and floating ops
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// CHECK-NEXT: simd Enable NEON instructions
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// CHECK-NEXT: fp16 Enable half-precision floating point
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// CHECK-NEXT: ras Enable Reliability, Availability and Serviceability extensions
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// CHECK-NEXT: fp16fml Enable full half-precision floating point fml instructions
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// CHECK-NEXT: bf16 Enable support for BFloat16 instructions
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// CHECK-NEXT: sb Enable v8.5a Speculation Barrier
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// CHECK-NEXT: i8mm Enable Matrix Multiply Int8 Extension
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// CHECK-NEXT: lob Enable Low Overhead Branch extensions
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// CHECK-NEXT: cdecp0 Coprocessor 0 ISA is CDEv1
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// CHECK-NEXT: cdecp1 Coprocessor 1 ISA is CDEv1
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// CHECK-NEXT: cdecp2 Coprocessor 2 ISA is CDEv1
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// CHECK-NEXT: cdecp3 Coprocessor 3 ISA is CDEv1
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// CHECK-NEXT: cdecp4 Coprocessor 4 ISA is CDEv1
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// CHECK-NEXT: cdecp5 Coprocessor 5 ISA is CDEv1
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// CHECK-NEXT: cdecp6 Coprocessor 6 ISA is CDEv1
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// CHECK-NEXT: cdecp7 Coprocessor 7 ISA is CDEv1
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// CHECK-NEXT: pacbti Enable Pointer Authentication and Branch Target Identification
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