derek.holloway
7502bf64a4
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116 lines
3.0 KiB
ArmAsm
116 lines
3.0 KiB
ArmAsm
# REQUIRES: loongarch
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# RUN: llvm-mc --filetype=obj --triple=loongarch32 -mattr=+relax --defsym ELF32=1 %s -o %t.32.o
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# RUN: llvm-mc --filetype=obj --triple=loongarch64 -mattr=+relax %s -o %t.64.o
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# RUN: ld.lld %t.32.o -o %t.32
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# RUN: llvm-objdump -d --no-show-raw-insn %t.32 | FileCheck --check-prefixes=RELAX32 %s
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# RUN: ld.lld %t.64.o -o %t.64
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# RUN: llvm-objdump -d --no-show-raw-insn %t.64 | FileCheck --check-prefixes=RELAX64 %s
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# RELAX32-LABEL: <_start>:
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## .LANCHOR0@tprel = 8
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# RELAX32-NEXT: addi.w $a0, $tp, 8
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# RELAX32-NEXT: ld.w $a1, $a0, 0
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# RELAX32-NEXT: ld.w $a2, $tp, 8
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## .a@tprel - 4 = 0x7fc
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# RELAX32-NEXT: addi.w $a1, $zero, 1
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# RELAX32-NEXT: addi.w $a1, $a1, 2
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# RELAX32-NEXT: st.w $a1, $tp, 2044
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## .a@tprel = 0x800
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# RELAX32-NEXT: lu12i.w $a0, 1
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# RELAX32-NEXT: add.w $a0, $a0, $tp
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# RELAX32-NEXT: addi.w $a0, $a0, -2048
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# RELAX64-LABEL: <_start>:
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## .LANCHOR0@tprel = 8
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# RELAX64-NEXT: addi.d $a0, $tp, 8
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# RELAX64-NEXT: ld.d $a1, $a0, 0
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# RELAX64-NEXT: ld.d $a2, $tp, 8
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## .a@tprel - 4 = 0x7fc
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# RELAX64-NEXT: addi.d $a1, $zero, 1
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# RELAX64-NEXT: addi.d $a1, $a1, 2
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# RELAX64-NEXT: st.d $a1, $tp, 2044
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## .a@tprel = 0x800
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# RELAX64-NEXT: lu12i.w $a0, 1
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# RELAX64-NEXT: add.d $a0, $a0, $tp
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# RELAX64-NEXT: addi.d $a0, $a0, -2048
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.macro add dst, src1, src2, src3
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.ifdef ELF32
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add.w \dst, \src1, \src2, \src3
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.else
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add.d \dst, \src1, \src2, \src3
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.endif
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.endm
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.macro inst op dst, src1, src2
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.ifdef ELF32
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.ifc \op, addi
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addi.w \dst, \src1, \src2
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.else; .ifc \op, ld
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ld.w \dst, \src1, \src2
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.else; .ifc \op, st
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st.w \dst, \src1, \src2
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.else; .ifc \op, ldptr
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ldptr.w \dst, \src1, \src2
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.else
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.error "Unknown op in ELF32 mode"
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.endif; .endif; .endif; .endif
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.else
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.ifc \op, addi
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addi.d \dst, \src1, \src2
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.else; .ifc \op, ld
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ld.d \dst, \src1, \src2
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.else; .ifc \op, st
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st.d \dst, \src1, \src2
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.else; .ifc \op, ldptr
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ldptr.d \dst, \src1, \src2
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.else
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.error "Unknown op in ELF64 mode"
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.endif; .endif; .endif; .endif
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.endif
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.endm
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.macro addi dst, src1, src2
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inst addi \dst, \src1, \src2
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.endm
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.macro ld dst, src1, src2
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inst ld \dst, \src1, \src2
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.endm
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.macro st dst, src1, src2
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inst st \dst, \src1, \src2
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.endm
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.macro ldptr dst, src1, src2
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inst ldptr \dst, \src1, \src2
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.endm
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_start:
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## Test instructions not in pairs.
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lu12i.w $a0, %le_hi20_r(.LANCHOR0)
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add $a0, $a0, $tp, %le_add_r(.LANCHOR0)
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addi $a0, $a0, %le_lo12_r(.LANCHOR0)
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ld $a1, $a0, 0
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ld $a2, $a0, %le_lo12_r(.LANCHOR0)
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## hi20(a-4) = hi20(0x7fc) = 0. relaxable
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## Test non-adjacent instructions.
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lu12i.w $a0, %le_hi20_r(a-4)
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addi $a1, $zero, 0x1
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add $a0, $a0, $tp, %le_add_r(a-4)
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addi $a1, $a1, 0x2
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st $a1, $a0, %le_lo12_r(a-4)
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## hi20(a) = hi20(0x800) = 1. not relaxable
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lu12i.w $a0, %le_hi20_r(a)
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add $a0, $a0, $tp, %le_add_r(a)
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addi $a0, $a0, %le_lo12_r(a)
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.section .tbss,"awT",@nobits
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.space 8
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.LANCHOR0:
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.space 0x800-8
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.globl a
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a:
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.zero 4
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