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111 lines
5.2 KiB
TableGen
111 lines
5.2 KiB
TableGen
//===- AArch64SchedPredNeoverse.td - AArch64 Sched Preds -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines scheduling predicate definitions that are used by the
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// AArch64 Neoverse processors.
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//
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//===----------------------------------------------------------------------===//
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// Auxiliary predicates.
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// Check for LSL shift == 0
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def NeoverseNoLSL : MCSchedPredicate<
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CheckAll<[CheckShiftLSL,
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CheckShiftBy0]>>;
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// Identify LDR/STR H/Q-form scaled (and potentially extended) FP instructions
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def NeoverseHQForm : MCSchedPredicate<
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CheckAll<[
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CheckAny<[CheckHForm, CheckQForm]>,
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CheckImmOperand<4, 1>]>>;
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// Identify LDR/STR Q-form scaled (and potentially extended) FP instructions
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def NeoverseQForm : MCSchedPredicate<
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CheckAll<[
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CheckAny<[CheckQForm]>,
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CheckImmOperand<4, 1>]>>;
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// Check if <Pd> == <Pg>
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def NeoversePdIsPgFn : TIIPredicate<
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"isNeoversePdSameAsPg",
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MCOpcodeSwitchStatement<
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[MCOpcodeSwitchCase<[BRKA_PPmP, BRKB_PPmP],
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MCReturnStatement<CheckSameRegOperand<1, 2>>>],
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MCReturnStatement<CheckSameRegOperand<0, 1>>>>;
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def NeoversePdIsPg : MCSchedPredicate<NeoversePdIsPgFn>;
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// Check if SVE INC/DEC (scalar), ALL, {1, 2, 4}
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def NeoverseCheapIncDec : MCSchedPredicate<
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CheckAll<[CheckOpcode<[
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INCB_XPiI, INCH_XPiI,
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INCW_XPiI, INCD_XPiI,
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DECB_XPiI, DECH_XPiI,
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DECW_XPiI, DECD_XPiI]>,
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CheckImmOperand<2, 31>,
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CheckAny<[
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CheckImmOperand<3, 1>,
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CheckImmOperand<3, 2>,
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CheckImmOperand<3, 4>]>]>>;
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// Identify "[SU]?(MADD|MSUB)L?" as the alias for "[SU]?(MUL|MNEG)L?".
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def NeoverseMULIdiomPred : MCSchedPredicate< // <op> Rd, Rs, Rv, ZR
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CheckAll<[CheckOpcode<
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[MADDWrrr, MADDXrrr,
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MSUBWrrr, MSUBXrrr,
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SMADDLrrr, UMADDLrrr,
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SMSUBLrrr, UMSUBLrrr]>,
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CheckIsReg3Zero]>>;
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def NeoverseZeroMove : MCSchedPredicate<
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CheckAny<[
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// MOV Wd, #0
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// MOV Xd, #0
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CheckAll<[CheckOpcode<[MOVZWi, MOVZXi]>,
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CheckIsImmOperand<1>,
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CheckImmOperand<1, 0>,
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CheckImmOperand<2, 0>]>,
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// MOV Wd, WZR
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// MOV Xd, XZR
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// MOV Wd, Wn
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// MOV Xd, Xn
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CheckAll<[CheckOpcode<[ORRWrs, ORRXrs]>,
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CheckAll<[CheckIsReg1Zero,
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CheckImmOperand<3, 0>]>]>,
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// FMOV Hd, WZR
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// FMOV Hd, XZR
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// FMOV Sd, WZR
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// FMOV Dd, XZR
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CheckAll<[CheckOpcode<[FMOVWHr, FMOVXHr,
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FMOVWSr, FMOVXDr]>,
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CheckIsReg1Zero]>,
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// MOVI Dd, #0
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// MOVI Vd.2D, #0
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CheckAll<[CheckOpcode<[MOVID, MOVIv2d_ns]>,
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CheckImmOperand<1, 0>]>,
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// MOV Zd, Zn
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CheckAll<[CheckOpcode<[ORR_ZZZ]>,
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CheckSameRegOperand<1, 2>]>,
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// MOV Vd, Vn
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CheckAll<[CheckOpcode<[ORRv16i8, ORRv8i8]>,
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CheckSameRegOperand<1, 2>]>,
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]>>;
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def NeoverseAllActivePredicate : MCSchedPredicate<
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CheckAny<[
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// PTRUE Pd, ALL
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// PTRUES Pd, ALL
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CheckAll<[
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CheckOpcode<[
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PTRUE_B, PTRUE_H, PTRUE_S, PTRUE_D,
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PTRUES_B, PTRUES_H, PTRUES_S, PTRUES_D]>,
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CheckIsImmOperand<1>,
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CheckImmOperand<1, 31>]>,
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]>>;
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