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69 lines
1.9 KiB
C++
69 lines
1.9 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#define GET_SDNODE_ENUM
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#include "AMDGPUGenSDNodeInfo.inc"
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namespace llvm {
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namespace AMDGPUISD {
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enum NodeType : unsigned {
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// Convert a unswizzled wave uniform stack address to an address compatible
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// with a vector offset for use in stack access.
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WAVE_ADDRESS = GENERATED_OPCODE_END,
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DOT4,
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MAD_U64_U32,
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MAD_I64_I32,
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TEXTURE_FETCH,
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R600_EXPORT,
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CONST_ADDRESS,
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/// This node is for VLIW targets and it is used to represent a vector
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/// that is stored in consecutive registers with the same channel.
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/// For example:
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/// |X |Y|Z|W|
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/// T0|v.x| | | |
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/// T1|v.y| | | |
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/// T2|v.z| | | |
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/// T3|v.w| | | |
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BUILD_VERTICAL_VECTOR,
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DUMMY_CHAIN,
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};
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} // namespace AMDGPUISD
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class AMDGPUSelectionDAGInfo : public SelectionDAGGenTargetInfo {
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public:
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AMDGPUSelectionDAGInfo();
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~AMDGPUSelectionDAGInfo() override;
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bool disableGenericCombines(CodeGenOptLevel OptLevel) const override {
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// Disable generic DAG combines at -O0 to preserve debuggability.
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// This prevents optimizations like constant reassociation that would
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// eliminate intermediate instructions users want to step through.
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return OptLevel == CodeGenOptLevel::None;
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}
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const char *getTargetNodeName(unsigned Opcode) const override;
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void verifyTargetNode(const SelectionDAG &DAG,
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const SDNode *N) const override;
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H
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