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85 lines
3.5 KiB
C++
85 lines
3.5 KiB
C++
//===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the NVPTX implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
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#include "NVPTX.h"
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#include "NVPTXRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "NVPTXGenInstrInfo.inc"
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namespace llvm {
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class NVPTXSubtarget;
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class NVPTXInstrInfo : public NVPTXGenInstrInfo {
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const NVPTXRegisterInfo RegInfo;
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virtual void anchor();
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public:
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explicit NVPTXInstrInfo(const NVPTXSubtarget &STI);
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const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
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/* The following virtual functions are used in register allocation.
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* They are not implemented because the existing interface and the logic
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* at the caller side do not work for the elementized vector load and store.
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*
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* virtual Register isLoadFromStackSlot(const MachineInstr *MI,
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* int &FrameIndex) const;
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* virtual Register isStoreToStackSlot(const MachineInstr *MI,
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* int &FrameIndex) const;
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* virtual void storeRegToStackSlot(
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* MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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* unsigned SrcReg, bool isKill, int FrameIndex,
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* const TargetRegisterClass *RC, Register VReg,
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* MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const;
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* virtual void loadRegFromStackSlot(
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* MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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* unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC,
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* const TargetRegisterInfo *TRI, Register VReg, unsigned SubReg = 0,
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* MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const;
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*/
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, Register DestReg, Register SrcReg,
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bool KillSrc, bool RenamableDest = false,
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bool RenamableSrc = false) const override;
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// Branch analysis.
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const override;
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private:
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bool invertPredicateBranchInstr(MachineBasicBlock &MBB) const;
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};
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} // namespace llvm
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#endif
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