derek.holloway
7502bf64a4
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116 lines
3.4 KiB
CMake
116 lines
3.4 KiB
CMake
add_llvm_component_group(RISCV)
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set(LLVM_TARGET_DEFINITIONS RISCV.td)
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tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
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tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
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tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler
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--specialize-decoders-per-bitwidth)
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tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
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tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
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tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM RISCVGenExegesis.inc -gen-exegesis)
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tablegen(LLVM RISCVGenSDNodeInfo.inc -gen-sd-node-info)
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set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
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tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
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tablegen(LLVM RISCVGenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
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-combiners="RISCVO0PreLegalizerCombiner")
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tablegen(LLVM RISCVGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
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-combiners="RISCVPreLegalizerCombiner")
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tablegen(LLVM RISCVGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
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-combiners="RISCVPostLegalizerCombiner")
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add_public_tablegen_target(RISCVCommonTableGen)
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add_llvm_target(RISCVCodeGen
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RISCVAsmPrinter.cpp
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RISCVCallingConv.cpp
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RISCVCodeGenPrepare.cpp
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RISCVConstantPoolValue.cpp
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RISCVDeadRegisterDefinitions.cpp
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RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
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RISCVFoldMemOffset.cpp
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RISCVFrameLowering.cpp
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RISCVGatherScatterLowering.cpp
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RISCVIndirectBranchTracking.cpp
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RISCVInsertReadWriteCSR.cpp
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RISCVInsertVSETVLI.cpp
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RISCVInsertWriteVXRM.cpp
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RISCVInstrInfo.cpp
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RISCVInterleavedAccess.cpp
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RISCVISelDAGToDAG.cpp
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RISCVISelLowering.cpp
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RISCVLandingPadSetup.cpp
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RISCVLateBranchOpt.cpp
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RISCVLoadStoreOptimizer.cpp
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RISCVMachineFunctionInfo.cpp
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RISCVMakeCompressible.cpp
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RISCVMachineScheduler.cpp
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RISCVMergeBaseOffset.cpp
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RISCVMoveMerger.cpp
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RISCVOptWInstrs.cpp
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RISCVPostRAExpandPseudoInsts.cpp
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RISCVPromoteConstant.cpp
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RISCVPushPopOptimizer.cpp
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RISCVRedundantCopyElimination.cpp
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RISCVRegisterInfo.cpp
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RISCVSelectionDAGInfo.cpp
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RISCVSubtarget.cpp
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RISCVTargetMachine.cpp
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RISCVTargetObjectFile.cpp
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RISCVTargetTransformInfo.cpp
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RISCVVectorMaskDAGMutation.cpp
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RISCVVectorPeephole.cpp
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RISCVVLOptimizer.cpp
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RISCVVMV0Elimination.cpp
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RISCVVSETVLIInfoAnalysis.cpp
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RISCVZacasABIFix.cpp
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RISCVZilsdOptimizer.cpp
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GISel/RISCVCallLowering.cpp
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GISel/RISCVInlineAsmLowering.cpp
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GISel/RISCVInstructionSelector.cpp
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GISel/RISCVLegalizerInfo.cpp
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GISel/RISCVPostLegalizerCombiner.cpp
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GISel/RISCVO0PreLegalizerCombiner.cpp
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GISel/RISCVPreLegalizerCombiner.cpp
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GISel/RISCVRegisterBankInfo.cpp
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LINK_COMPONENTS
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Analysis
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AsmPrinter
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CodeGen
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CodeGenTypes
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Core
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GlobalISel
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IPO
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MC
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Passes
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RISCVDesc
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RISCVInfo
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Scalar
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SelectionDAG
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Support
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Target
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TargetParser
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TransformUtils
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Vectorize
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ADD_TO_COMPONENT
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RISCV
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)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(MCA)
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add_subdirectory(TargetInfo)
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