TheRock/compiler/amd-llvm/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

//===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
//  This file describes the RISC-V V extension instruction formats.
//
//===----------------------------------------------------------------------===//

class RISCVVFormat<bits<3> val> {
  bits<3> Value = val;
}
def OPIVV : RISCVVFormat<0b000>;
def OPFVV : RISCVVFormat<0b001>;
def OPMVV : RISCVVFormat<0b010>;
def OPIVI : RISCVVFormat<0b011>;
def OPIVX : RISCVVFormat<0b100>;
def OPFVF : RISCVVFormat<0b101>;
def OPMVX : RISCVVFormat<0b110>;
def OPCFG : RISCVVFormat<0b111>;

class RISCVMOP<bits<2> val> {
  bits<2> Value = val;
}
def MOPLDUnitStride   : RISCVMOP<0b00>;
def MOPLDIndexedUnord : RISCVMOP<0b01>;
def MOPLDStrided      : RISCVMOP<0b10>;
def MOPLDIndexedOrder : RISCVMOP<0b11>;

def MOPSTUnitStride   : RISCVMOP<0b00>;
def MOPSTIndexedUnord : RISCVMOP<0b01>;
def MOPSTStrided      : RISCVMOP<0b10>;
def MOPSTIndexedOrder : RISCVMOP<0b11>;

class RISCVLUMOP<bits<5> val> {
  bits<5> Value = val;
}
def LUMOPUnitStride  : RISCVLUMOP<0b00000>;
def LUMOPUnitStrideMask : RISCVLUMOP<0b01011>;
def LUMOPUnitStrideWholeReg : RISCVLUMOP<0b01000>;
def LUMOPUnitStrideFF: RISCVLUMOP<0b10000>;

class RISCVSUMOP<bits<5> val> {
  bits<5> Value = val;
}
def SUMOPUnitStride  : RISCVSUMOP<0b00000>;
def SUMOPUnitStrideMask : RISCVSUMOP<0b01011>;
def SUMOPUnitStrideWholeReg : RISCVSUMOP<0b01000>;

class RISCVWidth<bits<4> val> {
  bits<4> Value = val;
}
def LSWidth8     : RISCVWidth<0b0000>;
def LSWidth16    : RISCVWidth<0b0101>;
def LSWidth32    : RISCVWidth<0b0110>;
def LSWidth64    : RISCVWidth<0b0111>;

class RVInstVSetiVLi<dag outs, dag ins, string opcodestr, string argstr>
    : RVInstIBase<OPCFG.Value, OPC_OP_V, outs, ins, opcodestr, argstr> {
  bits<5> uimm;
  bits<10> vtypei;

  let rs1 = uimm;

  let Inst{31} = 1;
  let Inst{30} = 1;
  let Inst{29-20} = vtypei;

  let Defs = [VL, VTYPE];
}

class RVInstVSetVLi<dag outs, dag ins, string opcodestr, string argstr>
    : RVInstIBase<OPCFG.Value, OPC_OP_V, outs, ins, opcodestr, argstr> {
  bits<11> vtypei;

  let Inst{31} = 0;
  let Inst{30-20} = vtypei;

  let Defs = [VL, VTYPE];
}

class RVInstVSetVL<dag outs, dag ins, string opcodestr, string argstr>
    : RVInstR<0b1000000, OPCFG.Value, OPC_OP_V, outs, ins, opcodestr, argstr> {
  let Defs = [VL, VTYPE];
}

class RVInstVBase<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                  string opcodestr, string argstr>
    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
  bits<5> vd;
  bit vm;

  let Inst{31-26} = funct6;
  let Inst{25} = vm;
  // Inst{24-15} provide by subclasses
  let Inst{14-12} = opv.Value;
  let Inst{11-7} = vd;
  let Inst{6-0} = OPC_OP_V.Value;

  let Uses = [VL, VTYPE];
  let VMConstraint = true;

  let UseNamedOperandTable = true;
}

class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
               string opcodestr, string argstr>
    : RVInstVBase<funct6, opv, outs, ins, opcodestr, argstr> {
  bits<5> vs2;
  bits<5> vs1;

  let Inst{24-20} = vs2;
  let Inst{19-15} = vs1;
}

class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                string opcodestr, string argstr>
    : RVInstVBase<funct6, opv, outs, ins, opcodestr, argstr> {
  bits<5> vs2;
  bits<5> rs1;

  let Inst{24-20} = vs2;
  let Inst{19-15} = rs1;
}

class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
                string argstr>
    : RVInstVBase<funct6, OPIVI, outs, ins, opcodestr, argstr> {
  bits<5> vs2;
  bits<5> imm;

  let Inst{24-20} = vs2;
  let Inst{19-15} = imm;
}

class RVInstVUnary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
                   dag ins, string opcodestr, string argstr>
    : RVInstVBase<funct6, opv, outs, ins, opcodestr, argstr> {
  bits<5> vs2;

  let Inst{24-20} = vs2;
  let Inst{19-15} = vs1;
}

class RVInstVUnaryRd<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
                     dag ins, string opcodestr, string argstr>
    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
  bits<5> rd;
  bit vm;
  bits<5> vs2;

  let Inst{31-26} = funct6;
  let Inst{25} = vm;
  let Inst{24-20} = vs2;
  let Inst{19-15} = vs1;
  let Inst{14-12} = opv.Value;
  let Inst{11-7} = rd;
  let Inst{6-0} = OPC_OP_V.Value;

  let Uses = [VL, VTYPE];

  let UseNamedOperandTable = true;
}

class RVInstVLoadBase<bits<3> nf, RISCVWidth width, RISCVMOP mop,
                      dag outs, dag ins, string opcodestr, string argstr>
    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
  bits<5> rs1;
  bits<5> vd;
  bit vm;

  let Inst{31-29} = nf;
  let Inst{28} = width.Value{3};
  let Inst{27-26} = mop.Value;
  let Inst{25} = vm;
  // Inst{24-20} provided by subclasses
  let Inst{19-15} = rs1;
  let Inst{14-12} = width.Value{2-0};
  let Inst{11-7} = vd;
  let Inst{6-0} = OPC_LOAD_FP.Value;

  let Uses = [VL, VTYPE];
  let VMConstraint = true;

  let UseNamedOperandTable = true;
}

class RVInstVLU<bits<3> nf, RISCVWidth width, RISCVLUMOP lumop, dag outs,
                dag ins, string opcodestr, string argstr>
    : RVInstVLoadBase<nf, width, MOPLDUnitStride, outs, ins, opcodestr,
                      argstr> {
  let Inst{24-20} = lumop.Value;
}

class RVInstVLS<bits<3> nf, RISCVWidth width, dag outs, dag ins,
                string opcodestr, string argstr>
    : RVInstVLoadBase<nf, width, MOPLDStrided, outs, ins, opcodestr, argstr> {
  bits<5> rs2;

  let Inst{24-20} = rs2;
}

class RVInstVLX<bits<3> nf, RISCVWidth width, RISCVMOP mop, dag outs, dag ins,
                string opcodestr, string argstr>
    : RVInstVLoadBase<nf, width, mop, outs, ins, opcodestr, argstr> {
  bits<5> vs2;

  let Inst{24-20} = vs2;
}

class RVInstVStoreBase<bits<3> nf, RISCVWidth width, RISCVMOP mop, dag outs,
                       dag ins, string opcodestr, string argstr>
    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
  bits<5> rs1;
  bits<5> vs3;
  bit vm;

  let Inst{31-29} = nf;
  let Inst{28} = width.Value{3};
  let Inst{27-26} = mop.Value;
  let Inst{25} = vm;
  // Inst{24-20} provided by subclasses
  let Inst{19-15} = rs1;
  let Inst{14-12} = width.Value{2-0};
  let Inst{11-7} = vs3;
  let Inst{6-0} = OPC_STORE_FP.Value;

  let Uses = [VL, VTYPE];

  let UseNamedOperandTable = true;
}

class RVInstVSU<bits<3> nf, RISCVWidth width, RISCVSUMOP sumop, dag outs,
                dag ins, string opcodestr, string argstr>
    : RVInstVStoreBase<nf, width, MOPSTUnitStride, outs, ins, opcodestr,
                       argstr> {
  let Inst{24-20} = sumop.Value;
}

class RVInstVSS<bits<3> nf, RISCVWidth width, dag outs, dag ins,
                string opcodestr, string argstr>
    : RVInstVStoreBase<nf, width, MOPSTStrided, outs, ins, opcodestr,
                       argstr> {
  bits<5> rs2;

  let Inst{24-20} = rs2;
}

class RVInstVSX<bits<3> nf, RISCVWidth width, RISCVMOP mop, dag outs, dag ins,
                string opcodestr, string argstr>
    : RVInstVStoreBase<nf, width, mop, outs, ins, opcodestr, argstr> {
  bits<5> vs2;

  let Inst{24-20} = vs2;
}